285 lines
7.9 KiB
C++
285 lines
7.9 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _RV32GC_H_
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#define _RV32GC_H_
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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#include <iss/arch/traits.h>
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#include <array>
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namespace iss {
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namespace arch {
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struct rv32gc;
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template<>
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struct traits<rv32gc> {
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constexpr static char const* const core_type = "RV32GC";
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enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
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constexpr static unsigned FP_REGS_SIZE = 64;
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enum reg_e {
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X0,
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X1,
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X2,
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X3,
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X4,
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X5,
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X6,
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X7,
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X8,
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X9,
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X10,
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X11,
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X12,
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X13,
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X14,
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X15,
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X16,
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X17,
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X18,
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X19,
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X20,
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X21,
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X22,
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X23,
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X24,
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X25,
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X26,
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X27,
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X28,
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X29,
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X30,
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X31,
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PC,
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F0,
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F1,
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F2,
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F3,
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F4,
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F5,
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F6,
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F7,
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F8,
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F9,
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F10,
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F11,
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F12,
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F13,
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F14,
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F15,
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F16,
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F17,
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F18,
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F19,
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F20,
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F21,
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F22,
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F23,
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F24,
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F25,
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F26,
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F27,
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F28,
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F29,
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F30,
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F31,
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FCSR,
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NUM_REGS,
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NEXT_PC=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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LAST_BRANCH,
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ICOUNT
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};
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using reg_t = uint32_t;
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using addr_t = uint32_t;
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using code_word_t = uint32_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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constexpr static unsigned reg_bit_width(unsigned r) {
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constexpr std::array<const uint32_t, 72> RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}};
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return RV32GC_reg_size[r];
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}
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constexpr static unsigned reg_byte_offset(unsigned r) {
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constexpr std::array<const uint32_t, 73> RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}};
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return RV32GC_reg_byte_offset[r];
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}
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e {FLAGS};
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enum mem_type_e {MEM, CSR, FENCE, RES};
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};
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struct rv32gc: public arch_if {
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using virt_addr_t = typename traits<rv32gc>::virt_addr_t;
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using phys_addr_t = typename traits<rv32gc>::phys_addr_t;
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using reg_t = typename traits<rv32gc>::reg_t;
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using addr_t = typename traits<rv32gc>::addr_t;
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rv32gc();
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~rv32gc();
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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/// deprecated
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void get_reg(short idx, std::vector<uint8_t>& value) override {}
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void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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bool get_flag(int flag) override {return false;}
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void set_flag(int, bool value) override {};
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/// deprecated
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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uint64_t get_icount() { return reg.icount;}
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inline bool should_stop() { return interrupt_sim; }
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if(addr.space != traits<rv32gc>::MEM ||
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addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
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return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
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} else
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return virt2phys(addr);
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}
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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inline
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uint32_t get_last_branch(){return reg.last_branch;}
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protected:
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struct RV32GC_regs {
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uint32_t X0 = 0;
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uint32_t X1 = 0;
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uint32_t X2 = 0;
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uint32_t X3 = 0;
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uint32_t X4 = 0;
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uint32_t X5 = 0;
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uint32_t X6 = 0;
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uint32_t X7 = 0;
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uint32_t X8 = 0;
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uint32_t X9 = 0;
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uint32_t X10 = 0;
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uint32_t X11 = 0;
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uint32_t X12 = 0;
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uint32_t X13 = 0;
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uint32_t X14 = 0;
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uint32_t X15 = 0;
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uint32_t X16 = 0;
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uint32_t X17 = 0;
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uint32_t X18 = 0;
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uint32_t X19 = 0;
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uint32_t X20 = 0;
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uint32_t X21 = 0;
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uint32_t X22 = 0;
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uint32_t X23 = 0;
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uint32_t X24 = 0;
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uint32_t X25 = 0;
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uint32_t X26 = 0;
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uint32_t X27 = 0;
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uint32_t X28 = 0;
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uint32_t X29 = 0;
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uint32_t X30 = 0;
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uint32_t X31 = 0;
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uint32_t PC = 0;
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uint64_t F0 = 0;
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uint64_t F1 = 0;
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uint64_t F2 = 0;
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uint64_t F3 = 0;
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uint64_t F4 = 0;
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uint64_t F5 = 0;
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uint64_t F6 = 0;
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uint64_t F7 = 0;
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uint64_t F8 = 0;
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uint64_t F9 = 0;
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uint64_t F10 = 0;
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uint64_t F11 = 0;
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uint64_t F12 = 0;
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uint64_t F13 = 0;
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uint64_t F14 = 0;
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uint64_t F15 = 0;
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uint64_t F16 = 0;
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uint64_t F17 = 0;
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uint64_t F18 = 0;
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uint64_t F19 = 0;
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uint64_t F20 = 0;
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uint64_t F21 = 0;
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uint64_t F22 = 0;
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uint64_t F23 = 0;
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uint64_t F24 = 0;
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uint64_t F25 = 0;
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uint64_t F26 = 0;
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uint64_t F27 = 0;
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uint64_t F28 = 0;
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uint64_t F29 = 0;
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uint64_t F30 = 0;
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uint64_t F31 = 0;
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uint32_t FCSR = 0;
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uint32_t NEXT_PC = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
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uint64_t icount = 0;
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} reg;
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std::array<address_type, 4> addr_mode;
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bool interrupt_sim=false;
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uint32_t get_fcsr(){return reg.FCSR;}
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void set_fcsr(uint32_t val){reg.FCSR = val;}
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};
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}
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}
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#endif /* _RV32GC_H_ */
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