67 lines
2.5 KiB
C++
67 lines
2.5 KiB
C++
/*******************************************************************************
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* Copyright (C) 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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#ifndef RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_
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#define RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_
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#include "cci_configuration"
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#include <sysc/kernel/sc_module.h>
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namespace sysc {
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class h_bridge : public sc_core::sc_module {
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public:
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SC_HAS_PROCESS(h_bridge);// NOLINT
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sc_core::sc_in<sc_dt::sc_logic> ha_i, la_i;
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sc_core::sc_in<sc_dt::sc_logic> hb_i, lb_i;
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sc_core::sc_in<sc_dt::sc_logic> hc_i, lc_i;
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sc_core::sc_out<double> va_o, vb_o, vc_o;
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cci::cci_param<double> vcc;
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h_bridge(const sc_core::sc_module_name &nm);
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virtual ~h_bridge();
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private:
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void ain_cb();
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void bin_cb();
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void cin_cb();
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void write_output(sc_dt::sc_logic h_i, sc_dt::sc_logic l_i, sc_core::sc_out<double> &v_o);
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};
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} /* namespace sysc */
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#endif /* RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_ */
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