eyck
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f69b529cab
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Fixed implementation of RV64 so that remaining riscv-test pass
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2019-01-10 10:35:20 +00:00 |
 Eyck Jentzsch
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58a446e6bc
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Refoctored to to move SystemC wrapper into riscv library
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2018-11-19 20:39:11 +01:00 |
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Eyck Jentzsch
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20b3665003
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Back-ported DVCon turorial changes
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2018-11-12 19:36:44 +01:00 |
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Eyck Jentzsch
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38099e3fc6
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Added ADC, H-Bridge and motor models, refactored project structure
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2018-07-28 09:45:49 +02:00 |
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Eyck Jentzsch
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bc7450dad2
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Added softfloat library into top level build system
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2018-04-24 10:26:55 +02:00 |
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Eyck Jentzsch
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38471b8193
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Added cycle estimator and remove deprecated functions
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2018-03-30 17:59:40 +02:00 |
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Eyck Jentzsch
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36be8b87f1
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Added simple example plugin creating instruction histogram
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2018-02-11 21:30:52 +00:00 |
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Eyck Jentzsch
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873e4257f2
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Restructured DBT function to encapsulate the compilation process
This should enable the implementation of multi-threading of the
compilation process
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2017-12-28 17:09:24 +01:00 |
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Eyck Jentzsch
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d8184abbcc
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Refactored file dependencies to decouple components
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2017-09-26 17:48:51 +02:00 |
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Eyck Jentzsch
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710d61e304
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Fixed target adapter to properly handle register reading
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2017-09-25 20:38:40 +02:00 |
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Eyck Jentzsch
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9a617dab57
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Restructured project
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2017-09-21 20:29:23 +02:00 |
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Eyck Jentzsch
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aa8c2138c6
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Added initial SystemC structure and removed easylogging
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2017-09-21 13:13:01 +02:00 |
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Eyck Jentzsch
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1cb492b594
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Renamed hart name and core wrapper name
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2017-08-29 16:56:57 +02:00 |
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Eyck Jentzsch
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4ee7118b70
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Initial commit
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2017-08-27 13:04:48 +02:00 |