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Changed SystemC model to model a platform in a system. Added dedicated

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UART Terminal connected via tlm_signals
This commit is contained in:
Eyck Jentzsch
2018-07-12 15:27:36 +02:00
parent a3baa45b00
commit fede5b2af1
19 changed files with 529 additions and 130 deletions
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30
riscv.sc/incl/sysc/General/system.h Normal file
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@ -0,0 +1,30 @@
/*
* system.h
*
* Created on: 11.07.2018
* Author: eyck
*/
#ifndef __SYSC_GENERAL_SYSTEM_H_
#define __SYSC_GENERAL_SYSTEM_H_
#include "sysc/SiFive/platform.h"
#include "sysc/General/terminal.h"
#include <systemc>
namespace sysc {
class system: sc_core::sc_module {
public:
system(sc_core::sc_module_name nm);
virtual ~system();
sc_core::sc_vector<tlm::tlm_signal<sc_dt::sc_logic>> s_gpio;
private:
sysc::platform i_platform;
sysc::terminal i_terminal;
};
}
#endif /* __SYSC_GENERAL_SYSTEM_H_ */

42
riscv.sc/incl/sysc/General/terminal.h Normal file
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@ -0,0 +1,42 @@
/*
* terminal.h
*
* Created on: 07.07.2018
* Author: eyck
*/
#ifndef RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_
#define RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_
#include "scc/signal_target_mixin.h"
#include "scc/signal_initiator_mixin.h"
#include "tlm/tlm_signal.h"
#include "cci_configuration"
#include <sysc/kernel/sc_module.h>
#include <memory>
namespace sysc {
class WsHandler;
class terminal: public sc_core::sc_module {
public:
scc::tlm_signal_logic_out tx_o;
scc::tlm_signal_logic_in rx_i;
terminal();
terminal(const sc_core::sc_module_name& nm);
virtual ~terminal();
cci::cci_param<bool> write_to_ws;
protected:
std::vector<uint8_t> queue;
void receive(tlm::tlm_signal_gp<sc_dt::sc_logic>& gp, sc_core::sc_time& delay);
std::shared_ptr<sysc::WsHandler> handler;
sc_core::sc_time last_tx_start=sc_core::SC_ZERO_TIME;
};
}
#endif /* RISCV_SC_INCL_SYSC_GENERAL_TERMINAL_H_ */

3
riscv.sc/incl/sysc/SiFive/clint.h
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@ -55,7 +55,8 @@ class core_complex;
class clint : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(clint);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<sc_core::sc_time> tlclk_i;
sc_core::sc_in<sc_core::sc_time> lfclk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_out<bool> mtime_int_o;
sc_core::sc_out<bool> msip_int_o;

3
riscv.sc/incl/sysc/SiFive/core_complex.h
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@ -109,7 +109,8 @@ public:
~core_complex();
inline void sync(uint64_t cycle) {
quantum_keeper.inc(curr_clk*(cycle-last_sync_cycle));
auto time = curr_clk*(cycle-last_sync_cycle);
quantum_keeper.inc(time);
if (quantum_keeper.need_sync()) {
wait(quantum_keeper.get_local_time());
quantum_keeper.reset();

21
riscv.sc/incl/sysc/SiFive/gpio.h
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@ -38,8 +38,10 @@
#define _GPIO_H_
#include "scc/tlm_target.h"
#include "scc/signal_target_mixin.h"
#include "scc/signal_initiator_mixin.h"
#include <tlm/tlm_signal.h>
#include "cci_configuration"
#include <sysc/communication/sc_signal_rv_ports.h>
namespace sysc {
@ -51,7 +53,15 @@ public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_inout_rv<32> pins_io;
// sc_core::sc_inout_rv<32> pins_io;
sc_core::sc_vector<scc::tlm_signal_logic_out> pins_o;
sc_core::sc_vector<scc::tlm_signal_logic_in> pins_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof0_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> iof1_o;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof0_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> iof1_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
@ -62,14 +72,13 @@ protected:
void clock_cb();
void reset_cb();
void update_pins();
void pins_cb();
void before_end_of_elaboration();
void pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp, sc_core::sc_time& delay);
void forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic>& gp);
void iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
sc_core::sc_time clk;
std::unique_ptr<gpio_regs> regs;
std::shared_ptr<sysc::WsHandler> handler;
private:
void update_value_reg();
};
} /* namespace sysc */

31
riscv.sc/incl/sysc/SiFive/platform.h
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@ -34,8 +34,8 @@
//
////////////////////////////////////////////////////////////////////////////////
#ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_
#ifndef _PLATFORM_H_
#define _PLATFORM_H_
#include "aon.h"
#include "clint.h"
@ -44,14 +44,15 @@
#include "prci.h"
#include "spi.h"
#include "uart.h"
#include <array>
#include <sysc/kernel/sc_module.h>
#include "core_complex.h"
#include "scc/memory.h"
#include "scc/router.h"
#include "scc/utilities.h"
#include "core_complex.h"
#include "tlm/tlm_signal_sockets.h"
#include <sysc/kernel/sc_module.h>
#include <array>
namespace sysc {
@ -59,6 +60,12 @@ class platform : public sc_core::sc_module {
public:
SC_HAS_PROCESS(platform);
sc_core::sc_vector<tlm::tlm_signal_initiator_socket<sc_dt::sc_logic>> pins_o;
sc_core::sc_vector<tlm::tlm_signal_target_socket<sc_dt::sc_logic>> pins_i;
platform(sc_core::sc_module_name nm);
private:
SiFive::core_complex i_core_complex;
scc::router<> i_router;
uart i_uart0, i_uart1;
@ -71,13 +78,15 @@ public:
scc::memory<512_MB, 32> i_mem_qspi;
scc::memory<128_kB, 32> i_mem_ram;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<sc_core::sc_time> s_tlclk;
sc_core::sc_signal<sc_core::sc_time> s_lfclk;
sc_core::sc_signal<bool> s_rst, s_mtime_int, s_msie_int;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_int, s_local_int;
sc_core::sc_vector<sc_core::sc_signal<bool, SC_MANY_WRITERS>> s_global_int, s_local_int;
sc_core::sc_signal<bool> s_core_int;
sc_core::sc_signal_rv<32> s_gpio_pins;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_dummy;
sc_core::sc_vector<scc::tlm_signal_bool_opt_in> s_dummy_sck_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> s_dummy_sck_o;
platform(sc_core::sc_module_name nm);
protected:
void gen_reset();
@ -87,4 +96,4 @@ protected:
} /* namespace sysc */
#endif /* SIMPLESYSTEM_H_ */
#endif /* _PLATFORM_H_ */

19
riscv.sc/incl/sysc/SiFive/uart.h
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@ -37,11 +37,14 @@
#ifndef _UART_H_
#define _UART_H_
#include "cci_configuration"
#include "scc/tlm_target.h"
#include "scc/signal_target_mixin.h"
#include "scc/signal_initiator_mixin.h"
#include <tlm/tlm_signal.h>
#include "cci_configuration"
namespace sysc {
class tlm_signal_uart_extension;
class uart_regs;
class WsHandler;
@ -50,18 +53,28 @@ public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
scc::tlm_signal_bool_out tx_o;
scc::tlm_signal_bool_in rx_i;
sc_core::sc_out<bool> irq_o;
cci::cci_param<bool> write_to_ws;
uart(sc_core::sc_module_name nm);
virtual ~uart() override;
cci::cci_param<bool> write_to_ws;
protected:
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
void update_irq();
void before_end_of_elaboration();
sc_core::sc_time clk;
std::unique_ptr<uart_regs> regs;
sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
std::vector<uint8_t> queue;
sysc::tlm_signal_uart_extension *rx_ext, *tx_ext;
std::shared_ptr<sysc::WsHandler> handler;
};

31
riscv.sc/incl/sysc/tlm_extensions.h Normal file
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@ -0,0 +1,31 @@
/*
* tlm_extensions.h
*
* Created on: 12.07.2018
* Author: eyck
*/
#ifndef RISCV_SC_INCL_SYSC_TLM_EXTENSIONS_H_
#define RISCV_SC_INCL_SYSC_TLM_EXTENSIONS_H_
#include "tlm/tlm_extensions.h"
namespace sysc {
struct tlm_signal_uart_extension : public tlm::tlm_unmanaged_extension<tlm_signal_uart_extension> {
struct uart_tx {
unsigned data_bits:4;
unsigned stop_bits:2;
bool parity:1;
unsigned baud_rate:24;
unsigned data;
} tx;
sc_core::sc_time start_time;
};
}
#endif /* RISCV_SC_INCL_SYSC_TLM_EXTENSIONS_H_ */