Fixed implementation of RV64 so that remaining riscv-test pass

2019-01-10 10:35:20 +00:00
parent d5d236bf10
commit f69b529cab
27 changed files with 19993 additions and 8967 deletions
--- a/riscv/gen_input/RV32IBase.core_desc
+++ b/riscv/gen_input/RV32IBase.core_desc
@ -8,7 +8,7 @@ InsructionSet RV32IBase {
    }
    
    address_spaces { 
-        MEM[8], CSR[XLEN], FENCE[XLEN]
+        MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
    }
                
    registers {