Fixed implementation of RV64 so that remaining riscv-test pass

riscv/gen_input/RV32IBase.core_desc

@@ -8,7 +8,7 @@ InsructionSet RV32IBase {
     }
     
     address_spaces { 
-        MEM[8], CSR[XLEN], FENCE[XLEN]
+        MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
     }
                 
     registers {