Initial RV64I verification

2017-11-23 14:48:18 +01:00
parent 7b7648d8cc
commit f1667c195a
13 changed files with 843 additions and 180 deletions
--- a/riscv/gen_input/RV64IBase.core_desc
+++ b/riscv/gen_input/RV64IBase.core_desc
@@ -39,7 +39,7 @@ InsructionSet RV64IBase extends RV32IBase {
 			encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
 			args_disass:"x%rd$d, x%rs1$d, %imm%";
 			if(rd != 0){
-				val res[32] <= X[rs1]{32} + imm{32};
+				val res[32] <= X[rs1]{32} + imm;
 				X[rd] <= sext(res);
 			} 
 		}