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Initial RV64I verification

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Eyck Jentzsch
2017-11-23 14:48:18 +01:00
parent 7b7648d8cc
commit f1667c195a
13 changed files with 843 additions and 180 deletions
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7
riscv/gen_input/RV32C.core_desc
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@@ -12,6 +12,13 @@ InsructionSet RV32CI {
PC[XLEN](is_pc)
}
instructions{
JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
if(rd!=0) X[rd] <= PC+4;
val ret[XLEN] <= X[rs1]+ imm;
PC<=ret& ~0x1;
}
C.ADDI4SPN { //(RES, imm=0)
encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
args_disass: "x%rd$d, 0x%imm$05x";