Refactored code generation to use custom templates
This commit is contained in:
parent
7c2539bff0
commit
c5a7adcef5
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@ -0,0 +1 @@
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/src-gen/
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@ -130,13 +130,13 @@ InsructionSet RV32CI {
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args_disass: "0x%imm$05x";
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args_disass: "0x%imm$05x";
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PC<=PC+imm;
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PC<=PC+imm;
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}
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}
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C.BEQZ(no_cont) {//(RV32)
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C.BEQZ(no_cont,cond) {//(RV32)
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encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
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encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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val rs1_idx[5] <= rs1+8;
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val rs1_idx[5] <= rs1+8;
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PC<=choose(X[rs1_idx]==0, PC+imm, PC+2);
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PC<=choose(X[rs1_idx]==0, PC+imm, PC+2);
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}
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}
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C.BNEZ(no_cont) {//(RV32)
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C.BNEZ(no_cont,cond) {//(RV32)
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encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
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encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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args_disass: "x(8+%rs1$d), 0x%imm$05x";
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val rs1_idx[5] <= rs1+8;
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val rs1_idx[5] <= rs1+8;
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@ -47,32 +47,32 @@ InsructionSet RV32IBase {
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PC<=new_pc & ~0x1;
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PC<=new_pc & ~0x1;
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}
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}
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}
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}
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BEQ(no_cont){
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BEQ(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
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PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
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}
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}
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BNE(no_cont){
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BNE(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
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PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
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}
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}
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BLT(no_cont){
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BLT(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
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PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
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}
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}
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BGE(no_cont) {
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BGE(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
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PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
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}
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}
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BLTU(no_cont) {
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BLTU(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
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PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
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}
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}
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BGEU(no_cont) {
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BGEU(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
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PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
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@ -0,0 +1,8 @@
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{
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'${coreDef.name}' : [<%instructions.each{instr -> %>
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{
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'name' : '${instr.name}',
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'delay' : ${generator.hasAttribute(instr.instruction, com.minres.coredsl.coreDsl.InstrAttribute.COND)?[1,1]:1
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},<%}%>
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]
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}
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@ -0,0 +1,164 @@
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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////////////////////////////////////////////////////////////////////////////////
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<%
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import com.minres.coredsl.coreDsl.Register
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import com.minres.coredsl.coreDsl.RegisterFile
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def getTypeSize(size){
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if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
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}
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%>
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#ifndef _${coreDef.name.toUpperCase()}_H_
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#define _${coreDef.name.toUpperCase()}_H_
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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#include <iss/arch/traits.h>
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#include <array>
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namespace iss {
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namespace arch {
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struct ${coreDef.name.toLowerCase()};
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template<>
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struct traits<${coreDef.name.toLowerCase()}> {
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enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
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enum reg_e {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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${reg.name}${it},<%
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}
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} else if(reg instanceof Register){ %>
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${reg.name},<%
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}
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}%>
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NUM_REGS,
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NEXT_${pc.name}=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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ICOUNT
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};
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using reg_t = uint${regDataWidth}_t;
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using addr_t = uint${addrDataWidth}_t;
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using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
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constexpr static unsigned reg_bit_width(unsigned r) {
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constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{{${regSizes.join(",")}}};
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return ${coreDef.name}_reg_size[r];
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}
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constexpr static unsigned reg_byte_offset(unsigned r) {
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constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{{${regOffsets.join(",")}}};
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return ${coreDef.name}_reg_byte_offset[r];
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}
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static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
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enum sreg_flag_e {FLAGS};
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enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
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};
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struct ${coreDef.name.toLowerCase()}: public arch_if {
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using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
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using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
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using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
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using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
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${coreDef.name.toLowerCase()}();
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~${coreDef.name.toLowerCase()}();
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void reset(uint64_t address=0) override;
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uint8_t* get_regs_base_ptr() override;
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/// deprecated
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void get_reg(short idx, std::vector<uint8_t>& value) override {}
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void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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bool get_flag(int flag) override {return false;}
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void set_flag(int, bool value) override {};
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/// deprecated
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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uint64_t get_icount() { return reg.icount;}
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inline phys_addr_t v2p(const iss::addr_t& addr){
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if(addr.space != traits<${coreDef.name.toLowerCase()}>::MEM ||
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addr.type == iss::address_type::PHYSICAL ||
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addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
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return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
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} else
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return virt2phys(addr);
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}
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virtual phys_addr_t virt2phys(const iss::addr_t& addr);
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virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
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protected:
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struct ${coreDef.name}_regs {<%
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allRegs.each { reg ->
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if( reg instanceof RegisterFile) {
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(reg.range.right..reg.range.left).each{%>
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uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
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}
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} else if(reg instanceof Register){ %>
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uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
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}
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}%>
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uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
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uint64_t icount = 0;
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} reg;
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std::array<address_type, 4> addr_mode;
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uint64_t cycles = 0;
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};
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}
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}
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#endif /* _${coreDef.name.toUpperCase()}_H_ */
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@ -0,0 +1,73 @@
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
|
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// modification, are permitted provided that the following conditions are met:
|
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|
//
|
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// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
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// this list of conditions and the following disclaimer in the documentation
|
||||||
|
// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
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|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "util/ities.h"
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#include <util/logging.h>
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#include <elfio/elfio.hpp>
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#include <iss/arch/${coreDef.name.toLowerCase()}.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ihex.h>
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#ifdef __cplusplus
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}
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#endif
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#include <fstream>
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#include <cstdio>
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#include <cstring>
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using namespace iss::arch;
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${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
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reg.icount=0;
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}
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${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}(){
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}
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void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
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for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
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reg.PC=address;
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reg.NEXT_PC=reg.PC;
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reg.trap_state=0;
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reg.machine_state=0x0;
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}
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||||||
|
|
||||||
|
uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
|
||||||
|
return reinterpret_cast<uint8_t*>(®);
|
||||||
|
}
|
||||||
|
|
||||||
|
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::v2p(const iss::addr_t& pc) {
|
||||||
|
return phys_addr_t(pc); //change logical address to physical address
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,323 @@
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are met:
|
||||||
|
//
|
||||||
|
// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer in the documentation
|
||||||
|
// and/or other materials provided with the distribution.
|
||||||
|
//
|
||||||
|
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
//
|
||||||
|
// Contributors:
|
||||||
|
// eyck@minres.com - initial API and implementation
|
||||||
|
//
|
||||||
|
//
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#include <iss/arch/${coreDef.name.toLowerCase()}.h>
|
||||||
|
#include <iss/arch/riscv_hart_msu_vp.h>
|
||||||
|
#include <iss/debugger/gdb_session.h>
|
||||||
|
#include <iss/debugger/server.h>
|
||||||
|
#include <iss/iss.h>
|
||||||
|
#include <iss/vm_base.h>
|
||||||
|
#include <util/logging.h>
|
||||||
|
|
||||||
|
#include <boost/format.hpp>
|
||||||
|
|
||||||
|
#include <iss/debugger/riscv_target_adapter.h>
|
||||||
|
#include <array>
|
||||||
|
|
||||||
|
namespace iss {
|
||||||
|
namespace ${coreDef.name.toLowerCase()} {
|
||||||
|
using namespace iss::arch;
|
||||||
|
using namespace llvm;
|
||||||
|
using namespace iss::debugger;
|
||||||
|
|
||||||
|
template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
|
||||||
|
public:
|
||||||
|
using super = typename vm::vm_base<ARCH>;
|
||||||
|
using virt_addr_t = typename super::virt_addr_t;
|
||||||
|
using phys_addr_t = typename super::phys_addr_t;
|
||||||
|
using code_word_t = typename super::code_word_t;
|
||||||
|
using addr_t = typename super::addr_t;
|
||||||
|
|
||||||
|
vm_impl();
|
||||||
|
|
||||||
|
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
|
||||||
|
|
||||||
|
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
|
||||||
|
|
||||||
|
target_adapter_if *accquire_target_adapter(server_if *srv) {
|
||||||
|
debugger_if::dbg_enabled = true;
|
||||||
|
if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
|
||||||
|
vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
|
||||||
|
return vm::vm_base<ARCH>::tgt_adapter;
|
||||||
|
}
|
||||||
|
|
||||||
|
protected:
|
||||||
|
using vm::vm_base<ARCH>::get_reg_ptr;
|
||||||
|
|
||||||
|
template <typename T> inline llvm::ConstantInt *size(T type) {
|
||||||
|
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
|
||||||
|
}
|
||||||
|
|
||||||
|
inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
|
||||||
|
unsigned size) const {
|
||||||
|
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
|
||||||
|
}
|
||||||
|
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
|
||||||
|
llvm::BasicBlock *) override;
|
||||||
|
|
||||||
|
void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
|
||||||
|
|
||||||
|
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||||
|
|
||||||
|
void gen_leave_trap(unsigned lvl);
|
||||||
|
|
||||||
|
void gen_wait(unsigned type);
|
||||||
|
|
||||||
|
void gen_trap_behavior(llvm::BasicBlock *) override;
|
||||||
|
|
||||||
|
void gen_trap_check(llvm::BasicBlock *bb);
|
||||||
|
|
||||||
|
|
||||||
|
inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
|
||||||
|
return this->builder.CreateLoad(get_reg_ptr(i), false);
|
||||||
|
}
|
||||||
|
|
||||||
|
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
|
||||||
|
llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
|
||||||
|
this->get_type(traits<ARCH>::XLEN));
|
||||||
|
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
|
||||||
|
}
|
||||||
|
|
||||||
|
// some compile time constants
|
||||||
|
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
|
||||||
|
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
|
||||||
|
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
|
||||||
|
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
|
||||||
|
|
||||||
|
using this_class = vm_impl<ARCH>;
|
||||||
|
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
|
||||||
|
code_word_t instr,
|
||||||
|
llvm::BasicBlock *bb);
|
||||||
|
std::array<compile_func, LUT_SIZE> lut;
|
||||||
|
|
||||||
|
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||||
|
std::array<compile_func, LUT_SIZE> lut_11;
|
||||||
|
|
||||||
|
std::array<compile_func*, 4> qlut;
|
||||||
|
|
||||||
|
std::array<const uint32_t, 4> lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } };
|
||||||
|
|
||||||
|
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
|
||||||
|
compile_func f) {
|
||||||
|
if (pos < 0) {
|
||||||
|
lut[idx] = f;
|
||||||
|
} else {
|
||||||
|
auto bitmask = 1UL << pos;
|
||||||
|
if ((mask & bitmask) == 0) {
|
||||||
|
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
|
||||||
|
} else {
|
||||||
|
if ((valid & bitmask) == 0) {
|
||||||
|
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
|
||||||
|
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
|
||||||
|
} else {
|
||||||
|
auto new_val = idx << 1;
|
||||||
|
if ((value & bitmask) != 0) new_val++;
|
||||||
|
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
|
||||||
|
|
||||||
|
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
|
||||||
|
if (pos >= 0) {
|
||||||
|
auto bitmask = 1UL << pos;
|
||||||
|
if ((mask & bitmask) == 0) {
|
||||||
|
lut_val = extract_fields(pos - 1, val, mask, lut_val);
|
||||||
|
} else {
|
||||||
|
auto new_val = lut_val << 1;
|
||||||
|
if ((val & bitmask) != 0) new_val++;
|
||||||
|
lut_val = extract_fields(pos - 1, val, mask, new_val);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return lut_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
private:
|
||||||
|
/****************************************************************************
|
||||||
|
* start opcode definitions
|
||||||
|
****************************************************************************/
|
||||||
|
struct InstructionDesriptor {
|
||||||
|
size_t length;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t mask;
|
||||||
|
compile_func op;
|
||||||
|
};
|
||||||
|
|
||||||
|
const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
|
||||||
|
/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
|
||||||
|
/* instruction ${instr.instruction.name} */
|
||||||
|
{${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
|
||||||
|
}};
|
||||||
|
|
||||||
|
/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
|
||||||
|
/* instruction ${idx}: ${instr.name} */
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){<%instr.code.eachLine{%>
|
||||||
|
${it}<%}%>
|
||||||
|
}
|
||||||
|
<%}%>
|
||||||
|
/****************************************************************************
|
||||||
|
* end opcode definitions
|
||||||
|
****************************************************************************/
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
|
||||||
|
llvm::BasicBlock *bb) {
|
||||||
|
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
|
||||||
|
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||||||
|
get_reg_ptr(traits<ARCH>::PC), true);
|
||||||
|
this->builder.CreateStore(
|
||||||
|
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||||||
|
this->gen_const(64U, 1)),
|
||||||
|
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||||||
|
pc = pc + ((instr & 3) == 3 ? 4 : 2);
|
||||||
|
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||||||
|
this->gen_sync(iss::POST_SYNC, instr_descr.size());
|
||||||
|
this->gen_trap_check(this->leave_blk);
|
||||||
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
|
||||||
|
volatile CODE_WORD x = insn;
|
||||||
|
insn = 2 * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
|
||||||
|
|
||||||
|
template <typename ARCH>
|
||||||
|
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
|
||||||
|
: vm::vm_base<ARCH>(core, core_id, cluster_id) {
|
||||||
|
qlut[0] = lut_00.data();
|
||||||
|
qlut[1] = lut_01.data();
|
||||||
|
qlut[2] = lut_10.data();
|
||||||
|
qlut[3] = lut_11.data();
|
||||||
|
for (auto instr : instr_descr) {
|
||||||
|
auto quantrant = instr.value & 0x3;
|
||||||
|
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH>
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock *>
|
||||||
|
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
|
||||||
|
// we fetch at max 4 byte, alignment is 2
|
||||||
|
code_word_t insn = 0;
|
||||||
|
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||||
|
phys_addr_t paddr(pc);
|
||||||
|
try {
|
||||||
|
uint8_t *const data = (uint8_t *)&insn;
|
||||||
|
paddr = this->core.v2p(pc);
|
||||||
|
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
|
||||||
|
auto res = this->core.read(paddr, 2, data);
|
||||||
|
if (res != iss::Ok) throw trap_access(1, pc.val);
|
||||||
|
if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
|
||||||
|
res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
auto res = this->core.read(paddr, 4, data);
|
||||||
|
if (res != iss::Ok) throw trap_access(1, pc.val);
|
||||||
|
}
|
||||||
|
} catch (trap_access &ta) {
|
||||||
|
throw trap_access(ta.id, pc.val);
|
||||||
|
}
|
||||||
|
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
|
||||||
|
// curr pc on stack
|
||||||
|
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
|
||||||
|
++inst_cnt;
|
||||||
|
auto lut_val = extract_fields(insn);
|
||||||
|
auto f = qlut[insn & 0x3][lut_val];
|
||||||
|
if (f == nullptr) {
|
||||||
|
f = &this_class::illegal_intruction;
|
||||||
|
}
|
||||||
|
return (this->*f)(pc, insn, this_block);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock *leave_blk) {
|
||||||
|
this->builder.SetInsertPoint(leave_blk);
|
||||||
|
this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
|
||||||
|
auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
|
||||||
|
this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
|
||||||
|
std::vector<llvm::Value *> args{
|
||||||
|
this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
|
||||||
|
};
|
||||||
|
this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
|
||||||
|
auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
|
||||||
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
|
||||||
|
std::vector<llvm::Value *> args{
|
||||||
|
this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
|
||||||
|
};
|
||||||
|
this->builder.CreateCall(this->mod->getFunction("wait"), args);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
|
||||||
|
this->builder.SetInsertPoint(trap_blk);
|
||||||
|
auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||||
|
std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
|
||||||
|
this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
|
||||||
|
this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
|
||||||
|
auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||||
|
this->builder.CreateRet(trap_addr_val);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock *bb) {
|
||||||
|
auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||||||
|
this->gen_cond_branch(this->builder.CreateICmp(
|
||||||
|
ICmpInst::ICMP_EQ, v,
|
||||||
|
llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||||||
|
bb, this->trap_blk, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace ${coreDef.name.toLowerCase()}
|
||||||
|
|
||||||
|
template <>
|
||||||
|
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
|
||||||
|
std::unique_ptr<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>> ret =
|
||||||
|
std::make_unique<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>>(*core, dump);
|
||||||
|
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace iss
|
||||||
|
|
@ -28,9 +28,6 @@
|
||||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
// POSSIBILITY OF SUCH DAMAGE.
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
//
|
//
|
||||||
// Created on: Tue Feb 06 17:18:49 UTC 2018
|
|
||||||
// * rv32imac.h Author: <CoreDSL Generator>
|
|
||||||
//
|
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
#ifndef _RV32IMAC_H_
|
#ifndef _RV32IMAC_H_
|
||||||
|
|
@ -49,7 +46,7 @@ struct rv32imac;
|
||||||
template<>
|
template<>
|
||||||
struct traits<rv32imac> {
|
struct traits<rv32imac> {
|
||||||
|
|
||||||
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
|
enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
|
||||||
|
|
||||||
enum reg_e {
|
enum reg_e {
|
||||||
X0,
|
X0,
|
||||||
|
|
@ -117,7 +114,7 @@ struct traits<rv32imac> {
|
||||||
|
|
||||||
enum sreg_flag_e {FLAGS};
|
enum sreg_flag_e {FLAGS};
|
||||||
|
|
||||||
enum mem_type_e {MEM,CSR,FENCE,RES};
|
enum mem_type_e {MEM, CSR, FENCE, RES};
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -28,9 +28,6 @@
|
||||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
// POSSIBILITY OF SUCH DAMAGE.
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
//
|
//
|
||||||
// Created on: Tue Feb 06 17:18:50 UTC 2018
|
|
||||||
// * rv64ia.h Author: <CoreDSL Generator>
|
|
||||||
//
|
|
||||||
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
#ifndef _RV64IA_H_
|
#ifndef _RV64IA_H_
|
||||||
|
|
@ -49,7 +46,7 @@ struct rv64ia;
|
||||||
template<>
|
template<>
|
||||||
struct traits<rv64ia> {
|
struct traits<rv64ia> {
|
||||||
|
|
||||||
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147746049,PGSIZE=4096,PGMASK=4095};
|
enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
|
||||||
|
|
||||||
enum reg_e {
|
enum reg_e {
|
||||||
X0,
|
X0,
|
||||||
|
|
@ -117,7 +114,7 @@ struct traits<rv64ia> {
|
||||||
|
|
||||||
enum sreg_flag_e {FLAGS};
|
enum sreg_flag_e {FLAGS};
|
||||||
|
|
||||||
enum mem_type_e {MEM,CSR,FENCE,RES};
|
enum mem_type_e {MEM, CSR, FENCE, RES};
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue