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Added initial SystemC structure and removed easylogging

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This commit is contained in:
Eyck Jentzsch
2017-09-21 13:13:01 +02:00
parent 7f819def67
commit aa8c2138c6
32 changed files with 1810 additions and 1174 deletions
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19
riscv/src/CMakeLists.txt
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@ -3,12 +3,21 @@ FILE(GLOB RiscVHeaders *.h)
set(LIB_HEADERS ${RiscVHeaders} )
set(LIB_SOURCES
iss/rv32imac.cpp
iss/rv64ia.cpp
internal/vm_rv32imac.cpp
internal/vm_rv64ia.cpp
sysc/core_complex.cpp
sysc/gpio.cpp
sysc/plic.cpp
sysc/platform.cpp
sysc/spi.cpp
sysc/uart.cpp
)
set(APP_HEADERS )
set(APP_SOURCES main.cpp)
set(APP_SOURCES main.cpp sc_main.cpp
)
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME riscv)
@ -33,10 +42,10 @@ target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} sc-components)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
#target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
#if(SCV_FOUND)
#target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
#endif(SCV_FOUND)
target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
if(SCV_FOUND)
target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
endif()
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
# Says how and where to install software

29
riscv/src/internal/vm_riscv.in.cpp
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@ -36,7 +36,7 @@
#include <iss/iss.h>
#include <iss/debugger/gdb_session.h>
#include <easylogging++.h>
#include <util/logging.h>
#include <memory>
#include <cstring>
@ -45,7 +45,7 @@
#include "iss/debugger/server.h"
#include <boost/format.hpp>
#include "../../incl/iss/arch/riscv_hart_msu_vp.h"
#include "iss/arch/riscv_hart_msu_vp.h"
namespace iss {
namespace CORE_DEF_NAME {
@ -225,6 +225,17 @@ protected:
ptrType);
}
inline
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false);
// } else {
// if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
// return this->loaded_regs[i];
// }
}
inline
void gen_set_pc(virt_addr_t pc){
llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
@ -393,7 +404,7 @@ void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
template<typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
auto* TRAP_val = this->gen_const(traits<ARCH>::XLEN, 0x80<<24| (cause<<16) | trap_id );
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
}
@ -510,7 +521,7 @@ namespace CORE_DEF_NAME {
template<typename ARCH>
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
LOG(TRACE)<<"reading target registers";
LOG(logging::TRACE)<<"reading target registers";
//return idx<0?:;
data.clear();
avail.clear();
@ -652,8 +663,8 @@ namespace CORE_DEF_NAME {
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length});
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val);
LOG(TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
LOG(logging::TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Ok;
}
@ -663,12 +674,12 @@ namespace CORE_DEF_NAME {
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
// TODO: check length of addr range
if(handle){
LOG(TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
LOG(logging::TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Ok;
}
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Err;
}

1228
riscv/src/internal/vm_rv32imac.cpp
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File diff suppressed because it is too large Load Diff

2
riscv/src/iss/rv32imac.cpp
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@ -34,7 +34,7 @@
////////////////////////////////////////////////////////////////////////////////
#include "util/ities.h"
#include <easylogging++.h>
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/rv32imac.h>

30
riscv/src/main.cpp
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@ -38,9 +38,8 @@
#include <iostream>
#include <iss/arch/rv32imac.h>
#ifndef WITHOUT_LLVM
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
#endif
#ifdef WITH_SYSTEMC
#include <sysc/kernel/sc_externs.h>
#endif
@ -48,8 +47,6 @@
namespace po= boost::program_options;
INITIALIZE_EASYLOGGINGPP
int main(int argc, char *argv[]) {
try{
/** Define and parse the program options
@ -63,17 +60,26 @@ int main(int argc, char *argv[]) {
// application code comes here //
iss::init_jit(argc, argv);
if(vm.count("systemc")){
//#ifdef WITH_SYSTEMC
// return sc_core::sc_elab_and_sim(argc, argv);
//#else
#ifdef WITH_SYSTEMC
return sc_core::sc_elab_and_sim(argc, argv);
#else
std::cerr<<"SystemC simulation is currently not supported, please rebuild with -DWITH_SYSTEMC"<<std::endl;
//#endif
#endif
} else {
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = vm.count("gdb-port")?
iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
iss::create<iss::arch::rv32imac>("rv32ima", dump);
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
@ -96,7 +102,7 @@ int main(int argc, char *argv[]) {
return cpu->start(vm["cycles"].as<int64_t>());
}
} catch(std::exception& e){
LOG(ERROR) << "Unhandled Exception reached the top of main: "
LOG(logging::ERROR) << "Unhandled Exception reached the top of main: "
<< e.what() << ", application will now exit" << std::endl;
return ERROR_UNHANDLED_EXCEPTION;
}

20
riscv/src/minres_rv.core_desc
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@ -2,9 +2,9 @@ import "RV32IBase.core_desc"
import "RV32M.core_desc"
import "RV32A.core_desc"
import "RV32C.core_desc"
//import "RV64IBase.core_desc"
import "RV64IBase.core_desc"
//import "RV64M.core_desc"
//import "RV64A.core_desc"
import "RV64A.core_desc"
Core RV32IMAC provides RV32IBase,RV32M,RV32A, RV32CI {
template:"vm_riscv.in.cpp";
@ -15,8 +15,8 @@ Core RV32IMAC provides RV32IBase,RV32M,RV32A, RV32CI {
PCLEN:=32;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
fencevmal:=2;
fencevmau:=3;
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000001;
PGSIZE := 4096; //1 << 12;
@ -24,15 +24,21 @@ Core RV32IMAC provides RV32IBase,RV32M,RV32A, RV32CI {
}
}
/*
Core RV64IMA provides RV64IBase, RV64M, RV64A {
Core RV64IA provides RV64IBase,RV64A {
template:"vm_riscv.in.cpp";
constants {
XLEN:=64;
XLEN2:=128;
XLEN_BIT_MASK:=0x3f;
PCLEN:=64;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b10000000000001000001000100000000;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
}
}
*/

83
riscv/src/sc_main.cpp Normal file
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@ -0,0 +1,83 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
/*
* sc_main.cpp
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sr_report/sr_report.h>
#include <boost/program_options.hpp>
#include <sysc/report.h>
#include <sstream>
#include <sysc/SiFive/platform.h>
using namespace sysc;
namespace po = boost::program_options;
namespace {
const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace
int sc_main(int argc, char* argv[]){
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG;
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing
///////////////////////////////////////////////////////////////////////////
po::options_description desc("Options");\
desc.add_options()\
("help,h", "Print help message")\
("debug,d", po::value<int>(), "set debug level")\
("trace,t", "trace SystemC signals");
po::variables_map vm;
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
// there are any problems
} catch(po::error& e){
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
}
///////////////////////////////////////////////////////////////////////////
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
sysc::tracer trace("simple_system", sysc::tracer::TEXT, vm.count("trace"));
///////////////////////////////////////////////////////////////////////////
// instantiate top level
///////////////////////////////////////////////////////////////////////////
platform i_simple_system("i_simple_system");
//sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM);
///////////////////////////////////////////////////////////////////////////
// run simulation
///////////////////////////////////////////////////////////////////////////
sc_start(sc_core::sc_time(100, sc_core::SC_NS));
if(!sc_end_of_simulation_invoked()) sc_stop();
return 0;
}

55
riscv/src/sysc/core_complex.cpp Normal file
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@ -0,0 +1,55 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#include <sysc/SiFive/core_complex.h>
namespace sysc {
namespace SiFive {
core_complex::core_complex(sc_core::sc_module_name name)
:sc_core::sc_module(name)
, NAMED(initiator)
, NAMED(rst_i){
// TODO Auto-generated constructor stub
}
core_complex::~core_complex() {
// TODO Auto-generated destructor stub
}
} /* namespace SiFive */
} /* namespace sysc */

50
riscv/src/sysc/gpio.cpp Normal file
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@ -0,0 +1,50 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/gpio.h"
#include "sysc/SiFive/gen/gpio_regs.h"
#include "sysc/utilities.h"
namespace sysc {
gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(gpio_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
gpio::~gpio() {
}
void gpio::clock_cb() {
}
void gpio::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

66
riscv/src/sysc/platform.cpp Normal file
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@ -0,0 +1,66 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
/*
* simplesystem.cpp
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#include <sysc/SiFive/platform.h>
namespace sysc {
platform::platform(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(i_master)
, NAMED(i_router, 4, 1)
, NAMED(i_uart)
, NAMED(i_spi)
, NAMED(i_gpio)
, NAMED(i_plic)
, NAMED(s_clk)
, NAMED(s_rst)
{
i_master.initiator(i_router.target[0]);
size_t i=0;
for(const auto& e: e300_plat_map){
i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size);
i++;
}
i_uart.clk_i(s_clk);
i_spi.clk_i(s_clk);
i_gpio.clk_i(s_clk);
i_plic.clk_i(s_clk);
s_clk.write(10_ns);
i_uart.rst_i(s_rst);
i_spi.rst_i(s_rst);
i_gpio.rst_i(s_rst);
i_plic.rst_i(s_rst);
i_master.rst_i(s_rst);
SC_THREAD(gen_reset);
}
void platform::gen_reset() {
s_rst=true;
wait(10_ns);
s_rst=false;
}
} /* namespace sysc */

51
riscv/src/sysc/plic.cpp Normal file
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@ -0,0 +1,51 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/plic.h"
#include "sysc/SiFive/gen/plic_regs.h"
#include "sysc/utilities.h"
namespace sysc {
plic::plic(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(plic_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
plic::~plic() {
}
void plic::clock_cb() {
this->clk=clk_i.read();
}
void plic::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

51
riscv/src/sysc/spi.cpp Normal file
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@ -0,0 +1,51 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/spi.h"
#include "sysc/SiFive/gen/spi_regs.h"
#include "sysc/utilities.h"
namespace sysc {
spi::spi(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
spi::~spi() {
}
void spi::clock_cb() {
this->clk=clk_i.read();
}
void spi::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

51
riscv/src/sysc/uart.cpp Normal file
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@ -0,0 +1,51 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/uart.h"
#include "sysc/SiFive/gen/uart_regs.h"
#include "sysc/utilities.h"
namespace sysc {
uart::uart(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
uart::~uart() {
}
void uart::clock_cb() {
this->clk=clk_i.read();
}
void uart::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */