Implemented basic HiFive1-like platform with PLL,tracing etc.

riscv/gen_input/templates/incl-CORENAME.h.gtl

@@ -162,6 +162,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
+    bool interrupt_sim=false;
 <%
 def fcsr = allRegs.find {it.name=='FCSR'}
 if(fcsr != null) {%>

riscv/gen_input/templates/src-CORENAME.cpp.gtl

@@ -1,21 +1,21 @@
 ////////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2017, MINRES Technologies GmbH
+// Copyright (C) 2017,2018 MINRES Technologies GmbH
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are met:
-// 
+//
 // 1. Redistributions of source code must retain the above copyright notice,
 //    this list of conditions and the following disclaimer.
-// 
+//
 // 2. Redistributions in binary form must reproduce the above copyright notice,
 //    this list of conditions and the following disclaimer in the documentation
 //    and/or other materials provided with the distribution.
-// 
+//
 // 3. Neither the name of the copyright holder nor the names of its contributors
 //    may be used to endorse or promote products derived from this software
 //    without specific prior written permission.
-// 
+//
 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

riscv/incl/iss/arch/rv32gc.h

@@ -179,6 +179,8 @@ struct rv32gc: public arch_if {
 
     uint64_t get_icount() { return reg.icount;}
 
+    bool should_stop(){return false;}
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if(addr.space != traits<rv32gc>::MEM ||
                 addr.type == iss::address_type::PHYSICAL ||

riscv/incl/iss/arch/rv32imac.h

@@ -144,8 +144,12 @@ struct rv32imac: public arch_if {
     /// deprecated
     void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
+    inline
     uint64_t get_icount() { return reg.icount;}
 
+    inline
+    bool should_stop() { return interrupt_sim;}
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if(addr.space != traits<rv32imac>::MEM ||
                 addr.type == iss::address_type::PHYSICAL ||
@@ -204,6 +208,7 @@ protected:
 
     std::array<address_type, 4> addr_mode;
     
+    bool interrupt_sim=false;
 
 	uint32_t get_fcsr(){return 0;}
 	void set_fcsr(uint32_t val){}

riscv/incl/iss/arch/rv64ia.h

@@ -146,6 +146,8 @@ struct rv64ia: public arch_if {
 
     uint64_t get_icount() { return reg.icount;}
 
+    bool should_stop(){return false;}
+
     inline phys_addr_t v2p(const iss::addr_t& addr){
         if(addr.space != traits<rv64ia>::MEM ||
                 addr.type == iss::address_type::PHYSICAL ||

riscv/src/iss/rv32gc.cpp

@@ -62,6 +62,7 @@ void rv32gc::reset(uint64_t address) {
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
     reg.machine_state=0x0;
+    reg.icount=0;
 }
 
 uint8_t* rv32gc::get_regs_base_ptr(){

riscv/src/iss/rv64ia.cpp

@@ -63,6 +63,7 @@ void rv64ia::reset(uint64_t address) {
     reg.NEXT_PC = reg.PC;
     reg.trap_state = 0;
     reg.machine_state = 0x3;
+    reg.icount=0;
 }
 
 uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }