Restructured project
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riscv.sc/incl/sysc/SiFive/uart.h
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42
riscv.sc/incl/sysc/SiFive/uart.h
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/*******************************************************************************
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* Copyright 2017 eyck@minres.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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* use this file except in compliance with the License. You may obtain a copy
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* of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations under
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* the License.
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******************************************************************************/
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#ifndef _UART_H_
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#define _UART_H_
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#include <sysc/tlm_target.h>
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namespace sysc {
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class uart_regs;
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class uart: public sc_core::sc_module, public tlm_target<> {
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public:
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SC_HAS_PROCESS(uart);
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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uart(sc_core::sc_module_name nm);
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virtual ~uart();
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protected:
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void clock_cb();
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void reset_cb();
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sc_core::sc_time clk;
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std::unique_ptr<uart_regs> regs;
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};
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} /* namespace sysc */
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#endif /* _UART_H_ */
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