VP/HIFIVE1-VP
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Restructured project

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This commit is contained in:
Eyck Jentzsch
2017-09-21 20:29:23 +02:00
parent aa8c2138c6
commit 9a617dab57
55 changed files with 16145 additions and 166 deletions
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11
riscv.sc/gen_input/fe310.rdl Normal file
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`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "plic.rdl"
addrmap e300_plat_t {
plic_regs plic @0x0C000000;
gpio_regs gpio @0x10012000;
uart_regs uart @0x10013000;
spi_regs spi @0x10014000;
} e300_plat;