Restructured project
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								riscv/gen_input/RV64M.core_desc
									
									
									
									
									
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							| @@ -0,0 +1,41 @@ | ||||
| import "RV64IBase.core_desc" | ||||
|  | ||||
| InsructionSet RV64M extends RV64IBase { | ||||
| 	instructions{        | ||||
| 		MULW{ | ||||
| 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; | ||||
| 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; | ||||
| 		    if(rd != 0){ | ||||
| 		    	X[rd]<= X[rs1] * X[rs2]; | ||||
| 		    } | ||||
| 		} | ||||
| 		DIVW { | ||||
| 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011; | ||||
| 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; | ||||
| 		    if(rd != 0){ | ||||
| 		    	X[rd] <= X[rs1]s / X[rs2]s; | ||||
| 		    } | ||||
| 		} | ||||
| 		DIVUW { | ||||
| 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; | ||||
| 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; | ||||
| 		    if(rd != 0){ | ||||
| 		    	X[rd] <= X[rs1] / X[rs2]; | ||||
| 		    } | ||||
| 		} | ||||
| 		REMW { | ||||
| 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011; | ||||
| 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; | ||||
| 		    if(rd != 0){ | ||||
| 		    	X[rd] <= X[rs1]s % X[rs2]s; | ||||
| 		    } | ||||
| 		} | ||||
| 		REMUW { | ||||
| 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011; | ||||
| 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; | ||||
| 		    if(rd != 0){ | ||||
| 		    	X[rd] <= X[rs1] % X[rs2]; | ||||
| 		    } | ||||
| 		} | ||||
| 	} | ||||
| } | ||||
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