Changed handling of disassembler output so that tarcing becomes possible
This commit is contained in:
parent
e67864c2e8
commit
9970303fa4
2
dbt-core
2
dbt-core
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@ -1 +1 @@
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Subproject commit 35d9bbfe6569f2412c2ff98cd3a554c4d750b3de
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Subproject commit 55b281a010a7cedc7ba23c3856a551a9ee314eb4
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@ -46,6 +46,11 @@
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#include "scc/initiator_mixin.h"
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#include "scc/traceable.h"
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class scv_tr_db;
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class scv_tr_stream;
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struct _scv_tr_generator_default_data;
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template < class T_begin, class T_end> class scv_tr_generator;
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namespace iss {
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class vm_if;
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namespace arch {
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@ -103,7 +108,7 @@ public:
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}
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}
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bool read_mem(uint64_t addr, unsigned length, uint8_t *const data);
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bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
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bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
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@ -113,6 +118,7 @@ public:
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void trace(sc_core::sc_trace_file *trf) override;
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void disass_output(uint64_t pc, const std::string instr);
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protected:
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void before_end_of_elaboration();
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void start_of_simulation();
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@ -125,6 +131,17 @@ protected:
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std::unique_ptr<iss::vm_if> vm;
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sc_core::sc_time curr_clk;
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iss::debugger::target_adapter_if* tgt_adapter;
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#ifdef WITH_SCV
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//! transaction recording database
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scv_tr_db *m_db;
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//! blocking transaction recording stream handle
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scv_tr_stream *stream_handle;
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//! transaction generator handle for blocking transactions
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scv_tr_generator<_scv_tr_generator_default_data,_scv_tr_generator_default_data> *instr_tr_handle;
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scv_tr_generator<uint64_t,_scv_tr_generator_default_data> *fetch_tr_handle;
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scv_tr_handle tr_handle;
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#endif
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};
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} /* namespace SiFive */
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@ -45,6 +45,9 @@
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#include "iss/debugger/encoderdecoder.h"
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#include "sysc/SiFive/core_complex.h"
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#ifdef WITH_SCV
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#include <scv.h>
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#endif
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namespace sysc {
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namespace SiFive {
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@ -52,21 +55,64 @@ namespace {
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iss::debugger::encoder_decoder encdec;
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}
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namespace {
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const char lvl[] = {'U', 'S', 'H', 'M'};
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const char *trap_str[] = {"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"Reserved",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"Reserved",
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"Store/AMO page fault"};
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const char *irq_str[] = {
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"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
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"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
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"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"};
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}
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class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
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public:
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using core_type = iss::arch::rv32imac;
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using base_type = iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>;
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using phys_addr_t = typename iss::arch::traits<iss::arch::rv32imac>::phys_addr_t;
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core_wrapper(core_complex *owner)
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: owner(owner) {}
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: owner(owner)
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{}
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uint32_t get_mode(){ return this->reg.machine_state; }
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base_type::hart_state<base_type::reg_t>& get_state() { return this->state; }
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void notify_phase(iss::arch_if::exec_phase phase);
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void disass_output(uint64_t pc, const std::string instr) override {
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#ifndef WITH_SCV
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std::stringstream s;
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s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
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CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
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#else
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owner->disass_output(pc,instr);
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#endif
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};
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iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
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if (addr.type & iss::DEBUG)
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return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
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else
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return owner->read_mem(addr.val, length, data) ? iss::Ok : iss::Err;
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else {
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return owner->read_mem(addr.val, length, data,addr.type && iss::FETCH) ? iss::Ok : iss::Err;
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}
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}
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iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
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@ -127,7 +173,14 @@ core_complex::core_complex(sc_core::sc_module_name name)
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, NAMED(dump_ir, false, this)
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext())
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, tgt_adapter(nullptr){
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, tgt_adapter(nullptr)
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#ifdef WITH_SCV
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, m_db(scv_tr_db::get_default_db())
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, stream_handle(nullptr)
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, instr_tr_handle(nullptr)
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, fetch_tr_handle(nullptr)
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#endif
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{
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initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = read_lut.getEntry(start);
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@ -167,6 +220,25 @@ void core_complex::before_end_of_elaboration() {
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void core_complex::start_of_simulation() {
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quantum_keeper.reset();
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if (elf_file.value.size() > 0) cpu->load_file(elf_file.value);
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#ifdef WITH_SCV
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if (stream_handle == NULL) {
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string basename(this->name());
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stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
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instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
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fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
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}
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#endif
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}
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void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
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#ifdef WITH_SCV
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if(tr_handle.is_active()) tr_handle.end_transaction();
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tr_handle = instr_tr_handle->begin_transaction();
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tr_handle.record_attribute("PC", pc);
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tr_handle.record_attribute("INSTR", instr_str);
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tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
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tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
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#endif
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}
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void core_complex::clk_cb() { curr_clk = clk_i.read(); }
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@ -181,7 +253,7 @@ void core_complex::run() {
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sc_core::sc_stop();
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}
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bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data) {
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bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
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auto lut_entry = read_lut.getEntry(addr);
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if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
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addr + length <= lut_entry.get_end_address() + 1) {
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@ -197,6 +269,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data)
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gp.set_data_length(length);
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gp.set_streaming_width(4);
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auto delay{quantum_keeper.get_local_time()};
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#ifdef WITH_SCV
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if(tr_handle.is_valid()){
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if(is_fetch && tr_handle.is_active()) tr_handle.end_transaction();
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auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
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gp.set_extension(preExt);
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}
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#endif
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initiator->b_transport(gp, delay);
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LOG(TRACE) << "read_mem(0x" << std::hex << addr << ") : " << data;
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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@ -435,11 +435,11 @@ public:
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virtual uint64_t leave_trap(uint64_t flags) override;
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void wait_until(uint64_t flags) override;
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virtual std::string get_additional_disass_info() {
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void disass_output(uint64_t pc, const std::string instr) override {
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std::stringstream s;
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s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
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<< std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
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return s.str();
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CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
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};
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protected:
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@ -28,7 +28,7 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Tue Sep 26 17:41:14 CEST 2017
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// Created on: Wed Oct 18 11:42:36 CEST 2017
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// * rv32imac.h Author: <CoreDSL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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@ -36,30 +36,19 @@
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#ifndef _RV32IMAC_H_
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#define _RV32IMAC_H_
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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#include <iss/arch/traits.h>
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namespace iss {
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namespace arch {
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class rv32imac;
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struct rv32imac;
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template <> class traits<rv32imac> {
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public:
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enum constants {
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XLEN = 32,
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XLEN2 = 64,
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XLEN_BIT_MASK = 31,
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PCLEN = 32,
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fence = 0,
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fencei = 1,
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fencevmal = 2,
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fencevmau = 3,
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MISA_VAL = 1075056897,
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PGSIZE = 4096,
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PGMASK = 4095
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};
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template<>
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struct traits<rv32imac> {
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enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
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enum reg_e {
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X0,
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@ -96,7 +85,7 @@ public:
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X31,
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PC,
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NUM_REGS,
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NEXT_PC = NUM_REGS,
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NEXT_PC=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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@ -107,64 +96,61 @@ public:
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using addr_t = uint32_t;
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using code_word_t = uint32_t; // TODO: check removal
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using code_word_t = uint32_t; //TODO: check removal
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using virt_addr_t = iss::typed_addr_t<iss::VIRTUAL>;
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using phys_addr_t = iss::typed_addr_t<iss::PHYSICAL>;
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constexpr static unsigned reg_bit_width(unsigned r) {
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const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64};
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const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
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return RV32IMAC_reg_size[r];
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}
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constexpr static unsigned reg_byte_offset(unsigned r) {
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const uint32_t RV32IMAC_reg_byte_offset[] = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48,
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52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100,
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104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160};
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const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
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return RV32IMAC_reg_byte_offset[r];
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}
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enum sreg_flag_e { FLAGS };
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enum sreg_flag_e {FLAGS};
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enum mem_type_e {MEM,CSR,FENCE,RES};
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enum mem_type_e { MEM, CSR, FENCE, RES };
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};
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class rv32imac : public arch_if {
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public:
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struct rv32imac: public arch_if {
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using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
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using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
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using reg_t = typename traits<rv32imac>::reg_t;
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using reg_t = typename traits<rv32imac>::reg_t;
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using addr_t = typename traits<rv32imac>::addr_t;
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rv32imac();
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~rv32imac() = default;
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void reset(uint64_t address = 0) override;
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void reset(uint64_t address=0) override;
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uint8_t *get_regs_base_ptr() override;
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uint8_t* get_regs_base_ptr() override;
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/// deprecated
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void get_reg(short idx, std::vector<uint8_t> &value) override {}
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void set_reg(short idx, const std::vector<uint8_t> &value) override {}
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void get_reg(short idx, std::vector<uint8_t>& value) override {}
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void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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bool get_flag(int flag) override { return false; }
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void set_flag(int, bool value) override{};
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bool get_flag(int flag) override {return false;}
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void set_flag(int, bool value) override {};
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/// deprecated
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
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void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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void notify_phase(exec_phase phase) override {
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if (phase == ISTART) {
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void notify_phase(exec_phase phase){
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if(phase==ISTART){
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++reg.icount;
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reg.PC = reg.NEXT_PC;
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reg.trap_state = reg.pending_trap;
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reg.PC=reg.NEXT_PC;
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reg.trap_state=reg.pending_trap;
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}
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}
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uint64_t get_icount() { return reg.icount; }
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uint64_t get_icount() { return reg.icount;}
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virtual phys_addr_t v2p(const iss::addr_t &pc);
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virtual phys_addr_t v2p(const iss::addr_t& pc);
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virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
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@ -208,6 +194,7 @@ protected:
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uint64_t icount;
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} reg;
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};
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}
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}
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#endif /* _RV32IMAC_H_ */
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@ -28,7 +28,7 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Tue Sep 26 17:41:14 CEST 2017
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// Created on: Wed Oct 18 11:42:36 CEST 2017
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// * rv64ia.h Author: <CoreDSL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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@ -36,30 +36,19 @@
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#ifndef _RV64IA_H_
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#define _RV64IA_H_
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#include <iss/arch/traits.h>
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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#include <iss/arch/traits.h>
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namespace iss {
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namespace arch {
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class rv64ia;
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struct rv64ia;
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template <> class traits<rv64ia> {
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public:
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enum constants {
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XLEN = 64,
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XLEN2 = 128,
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XLEN_BIT_MASK = 63,
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PCLEN = 64,
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fence = 0,
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fencei = 1,
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fencevmal = 2,
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fencevmau = 3,
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MISA_VAL = 2147750144,
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PGSIZE = 4096,
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PGMASK = 4095
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};
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template<>
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struct traits<rv64ia> {
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enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
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enum reg_e {
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X0,
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@ -96,7 +85,7 @@ public:
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X31,
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PC,
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NUM_REGS,
|
||||
NEXT_PC = NUM_REGS,
|
||||
NEXT_PC=NUM_REGS,
|
||||
TRAP_STATE,
|
||||
PENDING_TRAP,
|
||||
MACHINE_STATE,
|
||||
|
|
@ -107,63 +96,61 @@ public:
|
|||
|
||||
using addr_t = uint64_t;
|
||||
|
||||
using code_word_t = uint64_t; // TODO: check removal
|
||||
using code_word_t = uint64_t; //TODO: check removal
|
||||
|
||||
using virt_addr_t = iss::typed_addr_t<iss::VIRTUAL>;
|
||||
|
||||
using phys_addr_t = iss::typed_addr_t<iss::PHYSICAL>;
|
||||
|
||||
constexpr static unsigned reg_bit_width(unsigned r) {
|
||||
const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
|
||||
64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64};
|
||||
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
|
||||
return RV64IA_reg_size[r];
|
||||
}
|
||||
|
||||
constexpr static unsigned reg_byte_offset(unsigned r) {
|
||||
const uint32_t RV64IA_reg_byte_offset[] = {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96,
|
||||
104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200,
|
||||
208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296};
|
||||
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
|
||||
return RV64IA_reg_byte_offset[r];
|
||||
}
|
||||
|
||||
enum sreg_flag_e { FLAGS };
|
||||
enum sreg_flag_e {FLAGS};
|
||||
|
||||
enum mem_type_e {MEM,CSR,FENCE,RES};
|
||||
|
||||
enum mem_type_e { MEM, CSR, FENCE, RES };
|
||||
};
|
||||
|
||||
class rv64ia : public arch_if {
|
||||
public:
|
||||
struct rv64ia: public arch_if {
|
||||
|
||||
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
|
||||
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
|
||||
using reg_t = typename traits<rv64ia>::reg_t;
|
||||
using reg_t = typename traits<rv64ia>::reg_t;
|
||||
using addr_t = typename traits<rv64ia>::addr_t;
|
||||
|
||||
rv64ia();
|
||||
~rv64ia();
|
||||
|
||||
void reset(uint64_t address = 0) override;
|
||||
void reset(uint64_t address=0) override;
|
||||
|
||||
uint8_t *get_regs_base_ptr() override;
|
||||
uint8_t* get_regs_base_ptr() override;
|
||||
/// deprecated
|
||||
void get_reg(short idx, std::vector<uint8_t> &value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t> &value) override {}
|
||||
void get_reg(short idx, std::vector<uint8_t>& value) override {}
|
||||
void set_reg(short idx, const std::vector<uint8_t>& value) override {}
|
||||
/// deprecated
|
||||
bool get_flag(int flag) override { return false; }
|
||||
void set_flag(int, bool value) override{};
|
||||
bool get_flag(int flag) override {return false;}
|
||||
void set_flag(int, bool value) override {};
|
||||
/// deprecated
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{};
|
||||
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
|
||||
|
||||
void notify_phase(exec_phase phase) {
|
||||
if (phase == ISTART) {
|
||||
void notify_phase(exec_phase phase){
|
||||
if(phase==ISTART){
|
||||
++reg.icount;
|
||||
reg.PC = reg.NEXT_PC;
|
||||
reg.trap_state = reg.pending_trap;
|
||||
reg.PC=reg.NEXT_PC;
|
||||
reg.trap_state=reg.pending_trap;
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t get_icount() { return reg.icount; }
|
||||
uint64_t get_icount() { return reg.icount;}
|
||||
|
||||
virtual phys_addr_t v2p(const iss::addr_t &pc);
|
||||
virtual phys_addr_t v2p(const iss::addr_t& pc);
|
||||
|
||||
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
|
||||
|
||||
|
|
@ -207,6 +194,7 @@ protected:
|
|||
uint64_t icount;
|
||||
} reg;
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
#endif /* _RV64IA_H_ */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue