Changed handling of disassembler output so that tarcing becomes possible

dbt-core

@@ -1 +1 @@
-Subproject commit 35d9bbfe6569f2412c2ff98cd3a554c4d750b3de
+Subproject commit 55b281a010a7cedc7ba23c3856a551a9ee314eb4

riscv.sc/incl/sysc/SiFive/core_complex.h

@@ -46,6 +46,11 @@
 #include "scc/initiator_mixin.h"
 #include "scc/traceable.h"
 
+class scv_tr_db;
+class scv_tr_stream;
+struct _scv_tr_generator_default_data;
+template < class T_begin, class T_end> class scv_tr_generator;
+
 namespace iss {
 class vm_if;
 namespace arch {
@@ -103,7 +108,7 @@ public:
         }
     }
 
-    bool read_mem(uint64_t addr, unsigned length, uint8_t *const data);
+    bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
 
     bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
 
@@ -113,6 +118,7 @@ public:
 
     void trace(sc_core::sc_trace_file *trf) override;
 
+    void disass_output(uint64_t pc, const std::string instr);
 protected:
     void before_end_of_elaboration();
     void start_of_simulation();
@@ -125,6 +131,17 @@ protected:
     std::unique_ptr<iss::vm_if> vm;
     sc_core::sc_time curr_clk;
     iss::debugger::target_adapter_if* tgt_adapter;
+#ifdef WITH_SCV
+    //! transaction recording database
+    scv_tr_db *m_db;
+    //! blocking transaction recording stream handle
+    scv_tr_stream *stream_handle;
+    //! transaction generator handle for blocking transactions
+    scv_tr_generator<_scv_tr_generator_default_data,_scv_tr_generator_default_data> *instr_tr_handle;
+    scv_tr_generator<uint64_t,_scv_tr_generator_default_data> *fetch_tr_handle;
+    scv_tr_handle tr_handle;
+#endif
+
 };
 
 } /* namespace SiFive */

riscv.sc/src/sysc/core_complex.cpp

@@ -45,6 +45,9 @@
 #include "iss/debugger/encoderdecoder.h"
 #include "sysc/SiFive/core_complex.h"
 
+#ifdef WITH_SCV
+#include <scv.h>
+#endif
 
 namespace sysc {
 namespace SiFive {
@@ -52,21 +55,64 @@ namespace {
 iss::debugger::encoder_decoder encdec;
 
 }
+namespace {
+
+const char lvl[] = {'U', 'S', 'H', 'M'};
+
+const char *trap_str[] = {"Instruction address misaligned",
+                          "Instruction access fault",
+                          "Illegal instruction",
+                          "Breakpoint",
+                          "Load address misaligned",
+                          "Load access fault",
+                          "Store/AMO address misaligned",
+                          "Store/AMO access fault",
+                          "Environment call from U-mode",
+                          "Environment call from S-mode",
+                          "Reserved",
+                          "Environment call from M-mode",
+                          "Instruction page fault",
+                          "Load page fault",
+                          "Reserved",
+                          "Store/AMO page fault"};
+const char *irq_str[] = {
+    "User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
+    "User timer interrupt",    "Supervisor timer interrupt",    "Reserved", "Machine timer interrupt",
+    "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"};
+}
+
 class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
 public:
     using core_type = iss::arch::rv32imac;
     using base_type = iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>;
     using phys_addr_t = typename iss::arch::traits<iss::arch::rv32imac>::phys_addr_t;
     core_wrapper(core_complex *owner)
-    : owner(owner) {}
+    : owner(owner)
+    {}
+
+    uint32_t get_mode(){ return this->reg.machine_state; }
+
+    base_type::hart_state<base_type::reg_t>& get_state() { return this->state; }
 
     void notify_phase(iss::arch_if::exec_phase phase);
 
+    void disass_output(uint64_t pc, const std::string instr) override {
+#ifndef WITH_SCV
+        std::stringstream s;
+        s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
+          << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
+        CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
+#else
+        owner->disass_output(pc,instr);
+#endif
+    };
+
     iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
         if (addr.type & iss::DEBUG)
             return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
-        else
+        else {
-            return owner->read_mem(addr.val, length, data) ? iss::Ok : iss::Err;
+            return owner->read_mem(addr.val, length, data,addr.type && iss::FETCH) ? iss::Ok : iss::Err;
+        }
     }
 
     iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
@@ -127,7 +173,14 @@ core_complex::core_complex(sc_core::sc_module_name name)
 , NAMED(dump_ir, false, this)
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
-, tgt_adapter(nullptr){
+, tgt_adapter(nullptr)
+#ifdef WITH_SCV
+, m_db(scv_tr_db::get_default_db())
+, stream_handle(nullptr)
+, instr_tr_handle(nullptr)
+, fetch_tr_handle(nullptr)
+#endif
+{
 
     initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
         auto lut_entry = read_lut.getEntry(start);
@@ -167,6 +220,25 @@ void core_complex::before_end_of_elaboration() {
 void core_complex::start_of_simulation() {
     quantum_keeper.reset();
     if (elf_file.value.size() > 0) cpu->load_file(elf_file.value);
+#ifdef WITH_SCV
+        if (stream_handle == NULL) {
+            string basename(this->name());
+            stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db);
+            instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle);
+            fetch_tr_handle = new scv_tr_generator<uint64_t>("fetch", *stream_handle);
+        }
+#endif
+}
+
+void core_complex::disass_output(uint64_t pc, const std::string instr_str) {
+#ifdef WITH_SCV
+    if(tr_handle.is_active()) tr_handle.end_transaction();
+    tr_handle = instr_tr_handle->begin_transaction();
+    tr_handle.record_attribute("PC", pc);
+    tr_handle.record_attribute("INSTR", instr_str);
+    tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]);
+    tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value);
+#endif
 }
 
 void core_complex::clk_cb() { curr_clk = clk_i.read(); }
@@ -181,7 +253,7 @@ void core_complex::run() {
     sc_core::sc_stop();
 }
 
-bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data) {
+bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) {
     auto lut_entry = read_lut.getEntry(addr);
     if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE &&
         addr + length <= lut_entry.get_end_address() + 1) {
@@ -197,6 +269,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data)
         gp.set_data_length(length);
         gp.set_streaming_width(4);
         auto delay{quantum_keeper.get_local_time()};
+#ifdef WITH_SCV
+        if(tr_handle.is_valid()){
+            if(is_fetch && tr_handle.is_active()) tr_handle.end_transaction();
+            auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this);
+            gp.set_extension(preExt);
+        }
+#endif
         initiator->b_transport(gp, delay);
         LOG(TRACE) << "read_mem(0x" << std::hex << addr << ") : " << data;
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {

riscv/incl/iss/arch/riscv_hart_msu_vp.h

@@ -435,11 +435,11 @@ public:
     virtual uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
-    virtual std::string get_additional_disass_info() {
+    void disass_output(uint64_t pc, const std::string instr) override {
         std::stringstream s;
         s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
           << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
-        return s.str();
+        CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
     };
 
 protected:

riscv/incl/iss/arch/rv32imac.h

@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Tue Sep 26 17:41:14 CEST 2017
+// Created on: Wed Oct 18 11:42:36 CEST 2017
 //             *      rv32imac.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -36,30 +36,19 @@
 #ifndef _RV32IMAC_H_
 #define _RV32IMAC_H_
 
-#include <iss/arch/traits.h>
 #include <iss/arch_if.h>
 #include <iss/vm_if.h>
+#include <iss/arch/traits.h>
 
 namespace iss {
 namespace arch {
 
-class rv32imac;
+struct rv32imac;
 
-template <> class traits<rv32imac> {
+template<>
-public:
+struct traits<rv32imac> {
-    enum constants {
+
-        XLEN = 32,
+    enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
-        XLEN2 = 64,
-        XLEN_BIT_MASK = 31,
-        PCLEN = 32,
-        fence = 0,
-        fencei = 1,
-        fencevmal = 2,
-        fencevmau = 3,
-        MISA_VAL = 1075056897,
-        PGSIZE = 4096,
-        PGMASK = 4095
-    };
 
     enum reg_e {
         X0,
@@ -114,26 +103,23 @@ public:
     using phys_addr_t = iss::typed_addr_t<iss::PHYSICAL>;
 
     constexpr static unsigned reg_bit_width(unsigned r) {
-        const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
+        const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
-                                              32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32,
-                                              32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64};
         return RV32IMAC_reg_size[r];
     }
 
     constexpr static unsigned reg_byte_offset(unsigned r) {
-        const uint32_t RV32IMAC_reg_byte_offset[] = {0,   4,   8,   12,  16,  20,  24,  28,  32,  36,  40,  44,  48,
+        const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
-                                                     52,  56,  60,  64,  68,  72,  76,  80,  84,  88,  92,  96,  100,
-                                                     104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160};
         return RV32IMAC_reg_byte_offset[r];
     }
 
     enum sreg_flag_e {FLAGS};
 
     enum mem_type_e {MEM,CSR,FENCE,RES};
+
 };
 
-class rv32imac : public arch_if {
+struct rv32imac: public arch_if {
-public:
+
     using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
     using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
     using reg_t =  typename traits<rv32imac>::reg_t;
@@ -154,7 +140,7 @@ public:
     /// deprecated
     void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
-    void notify_phase(exec_phase phase) override {
+    void notify_phase(exec_phase phase){
         if(phase==ISTART){
             ++reg.icount;
             reg.PC=reg.NEXT_PC;
@@ -208,6 +194,7 @@ protected:
         uint64_t icount;
     } reg;
 };
+
 }
 }            
 #endif /* _RV32IMAC_H_ */

riscv/incl/iss/arch/rv64ia.h

@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Tue Sep 26 17:41:14 CEST 2017
+// Created on: Wed Oct 18 11:42:36 CEST 2017
 //             *      rv64ia.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -36,30 +36,19 @@
 #ifndef _RV64IA_H_
 #define _RV64IA_H_
 
-#include <iss/arch/traits.h>
 #include <iss/arch_if.h>
 #include <iss/vm_if.h>
+#include <iss/arch/traits.h>
 
 namespace iss {
 namespace arch {
 
-class rv64ia;
+struct rv64ia;
 
-template <> class traits<rv64ia> {
+template<>
-public:
+struct traits<rv64ia> {
-    enum constants {
+
-        XLEN = 64,
+    enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
-        XLEN2 = 128,
-        XLEN_BIT_MASK = 63,
-        PCLEN = 64,
-        fence = 0,
-        fencei = 1,
-        fencevmal = 2,
-        fencevmau = 3,
-        MISA_VAL = 2147750144,
-        PGSIZE = 4096,
-        PGMASK = 4095
-    };
 
     enum reg_e {
         X0,
@@ -114,25 +103,23 @@ public:
     using phys_addr_t = iss::typed_addr_t<iss::PHYSICAL>;
 
     constexpr static unsigned reg_bit_width(unsigned r) {
-        const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
+        const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
-                                            64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64};
         return RV64IA_reg_size[r];
     }
 
     constexpr static unsigned reg_byte_offset(unsigned r) {
-        const uint32_t RV64IA_reg_byte_offset[] = {0,   8,   16,  24,  32,  40,  48,  56,  64,  72,  80,  88,  96,
+        const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
-                                                   104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200,
-                                                   208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296};
         return RV64IA_reg_byte_offset[r];
     }
 
     enum sreg_flag_e {FLAGS};
 
     enum mem_type_e {MEM,CSR,FENCE,RES};
+
 };
 
-class rv64ia : public arch_if {
+struct rv64ia: public arch_if {
-public:
+
     using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
     using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
     using reg_t =  typename traits<rv64ia>::reg_t;
@@ -207,6 +194,7 @@ protected:
         uint64_t icount;
     } reg;
 };
+
 }
 }            
 #endif /* _RV64IA_H_ */