Cleanup of generated code

dbt-core

@@ -1 +1 @@
-Subproject commit 8bdb487d2e635db487c81ad745f49edf871369d3
+Subproject commit 8cad193b272cbaa656baf2499feb5a14e9ad0c00

riscv/incl/iss/arch/minrv_ima.h

@@ -1,36 +1,37 @@
-/*******************************************************************************
+////////////////////////////////////////////////////////////////////////////////
- * Copyright (C) 2017, MINRES Technologies GmbH
+// Copyright (C) 2017, MINRES Technologies GmbH
- * All rights reserved.
+// All rights reserved.
- * 
+// 
- * Redistribution and use in source and binary forms, with or without
+// Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
+// modification, are permitted provided that the following conditions are met:
- * 
+// 
- * 1. Redistributions of source code must retain the above copyright notice,
+// 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
+//    this list of conditions and the following disclaimer.
- * 
+// 
- * 2. Redistributions in binary form must reproduce the above copyright notice,
+// 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
+//    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
+//    and/or other materials provided with the distribution.
- * 
+// 
- * 3. Neither the name of the copyright holder nor the names of its contributors
+// 3. Neither the name of the copyright holder nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
+//    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
+//    without specific prior written permission.
- * 
+// 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+// POSSIBILITY OF SUCH DAMAGE.
- * 
+// 
- * Contributors:
+// Created on: Sun Aug 27 17:03:32 CEST 2017
- *       eyck@minres.com - initial API and implementation
+//             *      minrv_ima.h Author: <CoreDSL Generator>
- ******************************************************************************/
+//
+////////////////////////////////////////////////////////////////////////////////
 
 #ifndef _MINRV_IMA_H_
 #define _MINRV_IMA_H_
@@ -127,21 +128,19 @@ struct minrv_ima: public arch_if {
     minrv_ima();
     ~minrv_ima();
 
-    void reset(uint64_t address=0);
+    virtual void reset(uint64_t address=0) override;
 
-//    virtual void loadFile(std::string name, int type=-1);
+    virtual uint8_t* get_regs_base_ptr() override;
+    /// deprecated
+    virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
+    virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
+    /// deprecated
+    virtual bool get_flag(int flag) override {return false;}
+    virtual void set_flag(int, bool value) override {};
+    /// deprecated
+    virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
 
-    uint8_t* get_regs_base_ptr() override;
+    virtual void notify_phase(exec_phase phase){
-
-    void get_reg(short idx, std::vector<uint8_t>& value) override;
-    void set_reg(short idx, const std::vector<uint8_t>& value) override;
-
-    bool get_flag(int flag) override;
-    void set_flag(int, bool value) override;
-
-    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override;
-
-    void notify_phase(exec_phase phase){
         if(phase==ISTART){
             ++reg.icount;
             reg.PC=reg.NEXT_PC;

riscv/src/internal/vm_minrv_ima.cpp

@@ -30,6 +30,8 @@
 // 
 // Contributors:
 //       eyck@minres.com - initial API and implementation
+//
+//
 ////////////////////////////////////////////////////////////////////////////////
 
 #include <iss/iss.h>

riscv/src/internal/vm_riscv.in.cpp

@@ -30,6 +30,8 @@
 // 
 // Contributors:
 //       eyck@minres.com - initial API and implementation
+//
+//
 ////////////////////////////////////////////////////////////////////////////////
 
 #include <iss/iss.h>
@@ -356,14 +358,14 @@ std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst
     uint8_t* const data = (uint8_t*)&insn;
         paddr=this->core.v2p(pc);
         if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
-            auto res = this->core.read_mem(paddr, 2, data);
+            auto res = this->core.read(paddr, 2, data);
             if(res!=iss::Ok)
                 throw trap_access(1, pc.val);
             if((insn & 0x3) == 0x3){ // this is a 32bit instruction
-                res = this->core.read_mem(this->core.v2p(pc+2), 2, data+2);
+                res = this->core.read(this->core.v2p(pc+2), 2, data+2);
             }
     } else {
-            auto res = this->core.read_mem(paddr, 4, data);
+            auto res = this->core.read(paddr, 4, data);
             if(res!=iss::Ok)
                 throw trap_access(1, pc.val);
         }
@@ -371,7 +373,7 @@ std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst
         throw trap_access(ta.id, pc.val);
     }
     if(insn==0x0000006f)
-        throw vm::simulation_stopped(0);
+        throw simulation_stopped(0);
     // curr pc on stack
     typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
     ++inst_cnt;
@@ -563,7 +565,7 @@ namespace CORE_DEF_NAME {
             data.resize(sizeof(typename traits<ARCH>::reg_t));
             avail.resize(sizeof(typename traits<ARCH>::reg_t));
             std::fill(avail.begin(), avail.end(), 0xff);
-            vm->get_arch()->read_mem(a, data.size(), data.data());
+            vm->get_arch()->read(a, data.size(), data.data());
         }
         return data.size()>0?Ok:Err;
     }
@@ -574,7 +576,7 @@ namespace CORE_DEF_NAME {
             vm->get_arch()->set_reg(reg_no, data);
         else {
             typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65);
-            vm->get_arch()->write_mem(a, data.size(), data.data());
+            vm->get_arch()->write(a, data.size(), data.data());
         }
         return Ok;
     }
@@ -583,7 +585,7 @@ namespace CORE_DEF_NAME {
     status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
         auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
         auto f = [&]()->status {
-            return vm->get_arch()->read_mem(a, data.size(), data.data());
+            return vm->get_arch()->read(a, data.size(), data.data());
         };
         return srv->execute_syncronized(f);
 
@@ -592,7 +594,7 @@ namespace CORE_DEF_NAME {
     template<typename ARCH>
     status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
         auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
-        return srv->execute_syncronized(&arch_if::write_mem, vm->get_arch(), a, data.size(), data.data());
+        return srv->execute_syncronized(&arch_if::write, vm->get_arch(), a, data.size(), data.data());
     }
 
     template<typename ARCH>

riscv/src/iss/minrv_ima.cpp

@@ -70,78 +70,6 @@ uint8_t* minrv_ima::get_regs_base_ptr(){
     return reinterpret_cast<uint8_t*>(&reg);
 }
 
-void minrv_ima::get_reg(short idx, std::vector<uint8_t>& value) {
-    if(idx<traits<minrv_ima>::NUM_REGS){
-        value.resize(traits<minrv_ima>::reg_byte_offset(idx+1)-traits<minrv_ima>::reg_byte_offset(idx));
-        uint8_t* r_ptr= ((uint8_t*)&reg)+traits<minrv_ima>::reg_byte_offset(idx);
-        std::copy(r_ptr, r_ptr+sizeof(traits<minrv_ima>::reg_t), value.begin());
-    }
-}
-
-void minrv_ima::set_reg(short idx, const std::vector<uint8_t>& value) {
-    if(idx < traits<minrv_ima>::NUM_REGS){
-        uint8_t* r_ptr= ((uint8_t*)&reg)+traits<minrv_ima>::reg_byte_offset(idx);
-        std::copy(value.begin(), value.end(), r_ptr);
-    }
-}
-
-bool minrv_ima::get_flag(int flag){
-    return false;
-}
-
-void minrv_ima::set_flag(int flag, bool value){
-}
-
-void minrv_ima::update_flags(operations op, uint64_t r0, uint64_t r1){
-}
-
 minrv_ima::phys_addr_t minrv_ima::v2p(const iss::addr_t& pc) {
     return phys_addr_t(pc); //change logical address to physical address
 }
-
-using namespace ELFIO;
-
-/*
-void minrv_ima::loadFile(std::string name, int type) {
-    FILE* fp = fopen(name.c_str(), "r");
-    if(fp){
-        char buf[5];
-        auto n = fread(buf, 1,4,fp);
-        if(n!=4) throw std::runtime_error("input file has insufficient size");
-        buf[4]=0;
-        if(strcmp(buf+1, "ELF")==0){
-            fclose(fp);
-            //Create elfio reader
-            elfio reader;
-            // Load ELF data
-            if ( !reader.load( name ) ) throw std::runtime_error("could not process elf file");
-            // check elf properties
-            //TODO: fix ELFCLASS like:
-            // if ( reader.get_class() != ELFCLASS32 ) throw std::runtime_error("wrong elf class in file");
-            if ( reader.get_type() != ET_EXEC ) throw std::runtime_error("wrong elf type in file");
-            //TODO: fix machine type like:
-            // if ( reader.get_machine() != EM_RISCV ) throw std::runtime_error("wrong elf machine in file");
-            auto sec_num = reader.sections.size();
-            auto seg_num = reader.segments.size();
-            for ( int i = 0; i < seg_num; ++i ) {
-                const auto pseg = reader.segments[i];
-                const auto fsize=pseg->get_file_size();         // 0x42c/0x0
-                const auto seg_data=pseg->get_data();
-                if(fsize>0){
-                    this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, traits<minrv_ima>::MEM, pseg->get_virtual_address()), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
-                }
-            }
-        } else {
-            fseek(fp, 0, SEEK_SET);
-            if(type<0) throw std::runtime_error("a memory type needs to be specified for IHEX files");
-            IHexRecord irec;
-            while (Read_IHexRecord(&irec, fp) == IHEX_OK) {
-                this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, type, irec.address), irec.dataLen, irec.data);
-            }
-        }
-    } else {
-        LOG(ERROR)<<"Could not open input file "<<name;
-        throw std::runtime_error("Could not open input file");
-    }
-}
-*/