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C++11 refactoring

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This commit is contained in:
Eyck Jentzsch
2018-02-06 11:34:34 +00:00
parent cb8b5e6d4b
commit 7c2539bff0
14 changed files with 623 additions and 216 deletions
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72
riscv/incl/iss/arch/riscv_hart_msu_vp.h
View File

@@ -46,6 +46,7 @@
#include <util/ities.h>
#include <util/sparse_array.h>
#include <util/bit_field.h>
#include <array>
namespace iss {
namespace arch {
@@ -159,28 +160,29 @@ enum csr_name {
namespace {
const char lvl[] = {'U', 'S', 'H', 'M'};
std::array<const char, 4> lvl = { { 'U', 'S', 'H', 'M' } };
const char *trap_str[] = {"Instruction address misaligned", //0
"Instruction access fault", //1
"Illegal instruction", //2
"Breakpoint", //3
"Load address misaligned", //4
"Load access fault", //5
"Store/AMO address misaligned", //6
"Store/AMO access fault", //7
"Environment call from U-mode", //8
"Environment call from S-mode", //9
"Reserved", //a
"Environment call from M-mode", //b
"Instruction page fault", //c
"Load page fault", //d
"Reserved", //e
"Store/AMO page fault"}; //f
const char *irq_str[] = {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"};
std::array<const char*, 16> trap_str = { { ""
"Instruction address misaligned", //0
"Instruction access fault", //1
"Illegal instruction", //2
"Breakpoint", //3
"Load address misaligned", //4
"Load access fault", //5
"Store/AMO address misaligned", //6
"Store/AMO access fault", //7
"Environment call from U-mode", //8
"Environment call from S-mode", //9
"Reserved", //a
"Environment call from M-mode", //b
"Instruction page fault", //c
"Load page fault", //d
"Reserved", //e
"Store/AMO page fault" } };
std::array<const char*, 12> irq_str = { {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User external interrupt",
"Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
enum {
PGSHIFT = 12,
@@ -313,7 +315,7 @@ public:
void write_mstatus(T val, unsigned priv_lvl){
auto mask = get_mask(priv_lvl);
auto new_val = (mstatus & ~mask) | (val & mask);
auto new_val = (mstatus.st.value & ~mask) | (val & mask);
mstatus=new_val;
}
@@ -435,12 +437,12 @@ public:
const typename super::reg_t PGMASK = PGSIZE - 1;
constexpr reg_t get_irq_mask(size_t mode) {
const reg_t m[4] = {
0b000100010001, // U mode
0b001100110011, // S-mode
0,
0b101110111011 // M-mode
};
std::array<const reg_t,4> m = { {
0b000100010001,// U mode
0b001100110011,// S mode
0,
0b101110111011 // M mode
}};
return m[mode];
}
@@ -485,7 +487,7 @@ protected:
mem_type mem;
csr_type csr;
hart_state<reg_t> state;
vm_info vm[2];
std::array<vm_info,2> vm;
void update_vm_info();
unsigned to_host_wr_cnt = 0;
std::stringstream uart_buf;
@@ -552,11 +554,11 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
template <typename BASE> void riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
FILE *fp = fopen(name.c_str(), "r");
if (fp) {
char buf[5];
auto n = fread(buf, 1, 4, fp);
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
if (n != 4) throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if (strcmp(buf + 1, "ELF") == 0) {
if (strcmp(buf.data() + 1, "ELF") == 0) {
fclose(fp);
// Create elfio reader
ELFIO::elfio reader;
@@ -1209,10 +1211,10 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
// reset trap state
this->reg.machine_state = new_priv;
this->reg.trap_state = 0;
char buffer[32];
sprintf(buffer, "0x%016lx", addr);
std::array<char, 32> buffer;
sprintf(buffer.data(), "0x%016lx", addr);
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause])<<"' ("<<trap_id<<")"
<< " at address " << buffer << " occurred, changing privilege level from " << lvl[cur_priv]
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv]
<< " to " << lvl[new_priv];
update_vm_info();
return this->reg.NEXT_PC;

9
riscv/incl/iss/arch/rv32imac.h
View File

@@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Sat Dec 30 12:50:15 CET 2017
// Created on: Tue Feb 06 17:18:49 UTC 2018
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@@ -39,6 +39,7 @@
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
#include <array>
namespace iss {
namespace arch {
@@ -103,12 +104,12 @@ struct traits<rv32imac> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
constexpr std::array<const uint32_t, 38> RV32IMAC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
return RV32IMAC_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
constexpr std::array<const uint32_t, 39> RV32IMAC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160}};
return RV32IMAC_reg_byte_offset[r];
}
@@ -197,7 +198,7 @@ protected:
uint64_t icount = 0;
} reg;
address_type addr_mode[4];
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;

11
riscv/incl/iss/arch/rv64ia.h
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@@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Sat Dec 30 12:50:15 CET 2017
// Created on: Tue Feb 06 17:18:50 UTC 2018
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@@ -39,6 +39,7 @@
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
#include <array>
namespace iss {
namespace arch {
@@ -103,12 +104,12 @@ struct traits<rv64ia> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
constexpr std::array<const uint32_t, 38> RV64IA_reg_size{{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64}};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
constexpr std::array<const uint32_t, 39> RV64IA_reg_byte_offset{{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296}};
return RV64IA_reg_byte_offset[r];
}
@@ -197,10 +198,10 @@ protected:
uint64_t icount = 0;
} reg;
address_type addr_mode[4];
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;
};
}