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C++11 refactoring

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This commit is contained in:
Eyck Jentzsch
2018-02-06 11:34:34 +00:00
parent cb8b5e6d4b
commit 7c2539bff0
14 changed files with 623 additions and 216 deletions
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8
riscv/gen_input/RV32IBase.core_desc
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@ -41,7 +41,7 @@ InsructionSet RV32IBase {
val new_pc[XLEN] <= X[rs1]+ imm;
val align[XLEN] <= new_pc & 0x2;
if(align != 0){
raise(0, 0)
raise(0, 0);
} else {
if(rd!=0) X[rd] <= PC+4;
PC<=new_pc & ~0x1;
@ -160,7 +160,7 @@ InsructionSet RV32IBase {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
}
@ -169,7 +169,7 @@ InsructionSet RV32IBase {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
}
@ -178,7 +178,7 @@ InsructionSet RV32IBase {
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
}

1
riscv/gen_input/minres_rv.core_desc
View File

@ -6,6 +6,7 @@ import "RV64IBase.core_desc"
//import "RV64M.core_desc"
import "RV64A.core_desc"
Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
template:"vm_riscv.in.cpp";
constants {