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|
@ -0,0 +1,32 @@
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||||||
|
.DS_Store
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||||||
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/*.il
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||||||
|
/avr-instr.html
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||||||
|
/blink.S
|
||||||
|
/flash.*
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||||||
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/avr-gdb.cmd
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||||||
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||||||
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/Debug/
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/Reelease/
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/*.vcd
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/*.ods
|
||||||
|
/build/
|
||||||
|
/*.logs
|
||||||
|
language.settings.xml
|
||||||
|
/*.gtkw
|
||||||
|
/Debug wo LLVM/
|
||||||
|
/atmega.txdb
|
||||||
|
/atmega.txlgz
|
||||||
|
/atmega.txlog
|
||||||
|
/.??*bdb.d.0
|
||||||
|
/.??*bdb.i.0
|
||||||
|
/.??*bdb.t
|
||||||
|
/tmp/
|
||||||
|
/test1.elf
|
||||||
|
/logs/
|
||||||
|
/*.log
|
||||||
|
/.gdbinit
|
||||||
|
/*.out
|
|
@ -0,0 +1,15 @@
|
||||||
|
[submodule "dbt-core"]
|
||||||
|
path = dbt-core
|
||||||
|
url = https://minres.com/git/SystemC/DBT-Core.git
|
||||||
|
[submodule "sc-components"]
|
||||||
|
path = sc-components
|
||||||
|
url = https://minres.com/git/SystemC/SystemC-Components.git
|
||||||
|
[submodule "external/easyloggingpp"]
|
||||||
|
path = external/easyloggingpp
|
||||||
|
url = https://github.com/muflihun/easyloggingpp.git
|
||||||
|
[submodule "external/elfio"]
|
||||||
|
path = external/elfio
|
||||||
|
url = http://git.code.sf.net/p/elfio/code
|
||||||
|
[submodule "external/libGIS"]
|
||||||
|
path = external/libGIS
|
||||||
|
url = https://github.com/vsergeev/libGIS.git
|
|
@ -0,0 +1,27 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>dbt-riscv</name>
|
||||||
|
<comment></comment>
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
</projectDescription>
|
|
@ -0,0 +1,32 @@
|
||||||
|
cmake_minimum_required(VERSION 2.8.12)
|
||||||
|
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
|
||||||
|
|
||||||
|
### set the directory names of the submodules
|
||||||
|
set(GIT_SUBMODULES elfio libGIS sc-components)
|
||||||
|
set(GIT_SUBMODULE_DIR_sc-components .)
|
||||||
|
set(GIT_SUBMODULE_DIR_dbt-core .)
|
||||||
|
### set each submodules's commit or tag that is to be checked out
|
||||||
|
### (leave empty if you want master)
|
||||||
|
#set(GIT_SUBMODULE_VERSION_sc-comp 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd)
|
||||||
|
|
||||||
|
include(GNUInstallDirs)
|
||||||
|
include(cmake/Submodules.cmake)
|
||||||
|
|
||||||
|
#enable_testing()
|
||||||
|
|
||||||
|
if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" OR "${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang")
|
||||||
|
set(warnings "-Wall -Wextra -Werror")
|
||||||
|
set(CMAKE_CXX_FLAG_RELEASE "-O2 -DNDEBUG")
|
||||||
|
set(CMAKE_C_FLAG_RELEASE "-O2 -DNDEBUG")
|
||||||
|
set(CMAKE_CXX_FLAG_DEBUG "-Og")
|
||||||
|
set(CMAKE_C_FLAG_DEBUG "-Og")
|
||||||
|
elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
|
||||||
|
set(warnings "/W4 /WX /EHsc")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
FIND_PACKAGE(Threads)
|
||||||
|
|
||||||
|
add_subdirectory(external)
|
||||||
|
add_subdirectory(dbt-core)
|
||||||
|
add_subdirectory(sc-components)
|
||||||
|
add_subdirectory(riscv)
|
|
@ -0,0 +1,29 @@
|
||||||
|
BSD 3-Clause License
|
||||||
|
|
||||||
|
Copyright (c) 2016, MINRES Technologies GmbH
|
||||||
|
All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
* Neither the name of the copyright holder nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived from
|
||||||
|
this software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
@ -0,0 +1,42 @@
|
||||||
|
# JIT-ISS
|
||||||
|
A versatile Just-in-time (JIT) compiling instruction set simulator (ISS)
|
||||||
|
|
||||||
|
**JIT-ISS README**
|
||||||
|
|
||||||
|
This is currently a proof of concept and work in progress, so use at your own risk. It is currently set-up as an Eclipse CDT project and based on LLVM. To build it you need latest LLVM and Eclipse CDT version 4.6 aka Neon.
|
||||||
|
|
||||||
|
To build with SystemC the define WITH_SYSTEMC needs to be set. Then a simple proof-of-concept system is created. Mainly missing are platform peripherals and interrupt handling. It reaches about 5 MIPS in lock-step mode on a MacBook Pro (Core i7-4870HQ@2.5GHz) running in a Docker container.
|
||||||
|
|
||||||
|
JIT-ISS uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license
|
||||||
|
|
||||||
|
**What's missing**
|
||||||
|
|
||||||
|
* only AVR instruction set implemented but not verified
|
||||||
|
|
||||||
|
**Planned features**
|
||||||
|
|
||||||
|
* add platform peripherals
|
||||||
|
* timers
|
||||||
|
* gpio
|
||||||
|
* ext interrupt registers and functionality
|
||||||
|
* and more
|
||||||
|
|
||||||
|
**Quick start**
|
||||||
|
|
||||||
|
* you need to have a decent compiler, make and cmake installed
|
||||||
|
* install LLVM 3.9 or 4.0 according to http://apt.llvm.org/
|
||||||
|
* download and install SystemC from http://accellera.org/downloads/standards/systemc
|
||||||
|
* optionally download and install SystemC Verification Library (SCV) from Accelera into the same location
|
||||||
|
* checkout source from git
|
||||||
|
* start an out-of-source build like so (e.g. when using LLVM 3.9 and bash)
|
||||||
|
```
|
||||||
|
cd JIT-ISS
|
||||||
|
mkdir build
|
||||||
|
cd build
|
||||||
|
LLVM_HOME=/usr/lib/llvm-3.9 cmake ..
|
||||||
|
make
|
||||||
|
```
|
||||||
|
* if the SystemC installation is not to be found be cmake you can optionally specify the location by either setting the following environment variables pointing to the installation
|
||||||
|
- SYSTEMC_HOME
|
||||||
|
- SYSTEMC_PREFIX
|
||||||
|
|
|
@ -0,0 +1,20 @@
|
||||||
|
# Function to link between sub-projects
|
||||||
|
function(add_dependent_subproject subproject_name)
|
||||||
|
#if (NOT TARGET ${subproject_name}) # target unknown
|
||||||
|
if(NOT PROJECT_${subproject_name}) # var unknown because we build only this subproject
|
||||||
|
find_package(${subproject_name} CONFIG REQUIRED)
|
||||||
|
else () # we know the target thus we are doing a build from the top directory
|
||||||
|
include_directories(../${subproject_name}/incl)
|
||||||
|
endif ()
|
||||||
|
endfunction(add_dependent_subproject)
|
||||||
|
|
||||||
|
# Make sure we tell the topdir CMakeLists that we exist (if build from topdir)
|
||||||
|
get_directory_property(hasParent PARENT_DIRECTORY)
|
||||||
|
if(hasParent)
|
||||||
|
set(PROJECT_${PROJECT_NAME} true PARENT_SCOPE)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
# Function to link between sub-projects
|
||||||
|
function(add_dependent_header subproject_name)
|
||||||
|
include_directories(../${subproject_name}/incl)
|
||||||
|
endfunction(add_dependent_header)
|
|
@ -0,0 +1,24 @@
|
||||||
|
function(PrepareDocTarget)
|
||||||
|
|
||||||
|
# Configure the doxygen config file with current settings:
|
||||||
|
configure_file(documentation-config.doxygen.in ${CMAKE_CURRENT_BINARY_DIR}/documentation-config.doxygen @ONLY)
|
||||||
|
|
||||||
|
# Set the name of the target : "doc" if it doesn't already exist and "doc<projectname>" if it does.
|
||||||
|
# This way we make sure to have a single "doc" target. Either it is the one of the top directory or
|
||||||
|
# it is the one of the subproject that we are compiling alone.
|
||||||
|
set(DOC_TARGET_NAME "doc")
|
||||||
|
if(TARGET doc)
|
||||||
|
set(DOC_TARGET_NAME "doc${PROJECT_NAME}")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
add_custom_target(${DOC_TARGET_NAME} ${TARGET_ALL}
|
||||||
|
${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/documentation-config.doxygen
|
||||||
|
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
|
||||||
|
COMMENT "Generating API documentation using doxygen for ${PROJECT_NAME}" VERBATIM)
|
||||||
|
|
||||||
|
set(INSTALL_DOC_DIR ${CMAKE_BINARY_DIR}/doc/${PROJECT_NAME}/html)
|
||||||
|
file(MAKE_DIRECTORY ${INSTALL_DOC_DIR}) # needed for install
|
||||||
|
|
||||||
|
install(DIRECTORY ${INSTALL_DOC_DIR} DESTINATION share/${PROJECT_NAME}-${VERSION_MAJOR} COMPONENT doc)
|
||||||
|
|
||||||
|
endfunction()
|
|
@ -0,0 +1,91 @@
|
||||||
|
SET(_SYSTEMC_HINTS
|
||||||
|
"[HKEY_LOCAL_MACHINE\\SOFTWARE\\SystemC\\2.2;SystemcHome]/include"
|
||||||
|
${SYSTEMC_PREFIX}/include
|
||||||
|
${SYSTEMC_PREFIX}/lib
|
||||||
|
${SYSTEMC_PREFIX}/lib-linux
|
||||||
|
${SYSTEMC_PREFIX}/lib-linux64
|
||||||
|
${SYSTEMC_PREFIX}/lib-macos
|
||||||
|
$ENV{SYSTEMC_PREFIX}/include
|
||||||
|
$ENV{SYSTEMC_PREFIX}/lib
|
||||||
|
$ENV{SYSTEMC_PREFIX}/lib-linux
|
||||||
|
$ENV{SYSTEMC_PREFIX}/lib-linux64
|
||||||
|
$ENV{SYSTEMC_PREFIX}/lib-macos
|
||||||
|
$ENV{SYSTEMC_HOME}/include
|
||||||
|
$ENV{SYSTEMC_HOME}/lib
|
||||||
|
$ENV{SYSTEMC_HOME}/lib-linux
|
||||||
|
$ENV{SYSTEMC_HOME}/lib-linux64
|
||||||
|
$ENV{SYSTEMC_HOME}/lib-macos
|
||||||
|
${CMAKE_INSTALL_PREFIX}/include
|
||||||
|
${CMAKE_INSTALL_PREFIX}/lib
|
||||||
|
${CMAKE_INSTALL_PREFIX}/lib-linux
|
||||||
|
${CMAKE_INSTALL_PREFIX}/lib-linux64
|
||||||
|
${CMAKE_INSTALL_PREFIX}/lib-macos
|
||||||
|
)
|
||||||
|
SET(_SYSTEMC_PATHS
|
||||||
|
/usr/include/systemc
|
||||||
|
/usr/lib
|
||||||
|
/usr/lib-linux
|
||||||
|
/usr/lib-linux64
|
||||||
|
/usr/lib-macos
|
||||||
|
/usr/local/include/sysc
|
||||||
|
/usr/local/lib
|
||||||
|
/usr/local/lib-linux
|
||||||
|
/usr/local/lib-linux64
|
||||||
|
/usr/local/lib-macos
|
||||||
|
)
|
||||||
|
FIND_FILE(_SYSTEMC_HEADER_FILE
|
||||||
|
NAMES systemc
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
PATH_SUFFIXES sysc/kernel
|
||||||
|
)
|
||||||
|
|
||||||
|
FIND_FILE(_SCV_HEADER_FILE
|
||||||
|
NAMES scv.h
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
PATH_SUFFIXES sysc/kernel
|
||||||
|
)
|
||||||
|
|
||||||
|
if(NOT _SYSTEMC_HEADER_FILE STREQUAL _SYSTEMC_HEADER_FILE-NOTFOUND)
|
||||||
|
set(SystemC_FOUND TRUE)
|
||||||
|
endif(NOT _SYSTEMC_HEADER_FILE STREQUAL _SYSTEMC_HEADER_FILE-NOTFOUND)
|
||||||
|
|
||||||
|
if(NOT _SCV_HEADER_FILE STREQUAL _SCV_HEADER_FILE-NOTFOUND)
|
||||||
|
set(SCV_FOUND TRUE)
|
||||||
|
endif(NOT _SCV_HEADER_FILE STREQUAL _SCV_HEADER_FILE-NOTFOUND)
|
||||||
|
|
||||||
|
FIND_PATH(SystemC_INCLUDE_DIRS
|
||||||
|
NAMES systemc.h
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
)
|
||||||
|
|
||||||
|
FIND_PATH(SystemC_LIBRARY_DIR
|
||||||
|
NAMES libsystemc.a
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
)
|
||||||
|
|
||||||
|
FIND_PATH(SCV_INCLUDE_DIRS
|
||||||
|
NAMES scv.h
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
)
|
||||||
|
|
||||||
|
FIND_PATH(SCV_LIBRARY_DIRS
|
||||||
|
NAMES libscv.a
|
||||||
|
HINTS ${_SYSTEMC_HINTS}
|
||||||
|
PATHS ${_SYSTEMC_PATHS}
|
||||||
|
)
|
||||||
|
|
||||||
|
if(SystemC_FOUND)
|
||||||
|
set(SystemC_LIBRARIES systemc)
|
||||||
|
message(STATUS "SystemC header files are taken from ${SystemC_INCLUDE_DIRS}")
|
||||||
|
message(STATUS "SystemC library is taken from ${SystemC_LIBRARY_DIR}")
|
||||||
|
if(SCV_FOUND)
|
||||||
|
set(SCV_LIBRARIES scv)
|
||||||
|
message(STATUS "SCV header files are taken from ${SCV_INCLUDE_DIRS}")
|
||||||
|
message(STATUS "SCV library is taken from ${SCV_LIBRARY_DIRS}")
|
||||||
|
endif(SCV_FOUND)
|
||||||
|
endif(SystemC_FOUND)
|
|
@ -0,0 +1,130 @@
|
||||||
|
# - Returns a version string from Git
|
||||||
|
#
|
||||||
|
# These functions force a re-configure on each git commit so that you can
|
||||||
|
# trust the values of the variables in your build system.
|
||||||
|
#
|
||||||
|
# get_git_head_revision(<refspecvar> <hashvar> [<additional arguments to git describe> ...])
|
||||||
|
#
|
||||||
|
# Returns the refspec and sha hash of the current head revision
|
||||||
|
#
|
||||||
|
# git_describe(<var> [<additional arguments to git describe> ...])
|
||||||
|
#
|
||||||
|
# Returns the results of git describe on the source tree, and adjusting
|
||||||
|
# the output so that it tests false if an error occurs.
|
||||||
|
#
|
||||||
|
# git_get_exact_tag(<var> [<additional arguments to git describe> ...])
|
||||||
|
#
|
||||||
|
# Returns the results of git describe --exact-match on the source tree,
|
||||||
|
# and adjusting the output so that it tests false if there was no exact
|
||||||
|
# matching tag.
|
||||||
|
#
|
||||||
|
# Requires CMake 2.6 or newer (uses the 'function' command)
|
||||||
|
#
|
||||||
|
# Original Author:
|
||||||
|
# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
|
||||||
|
# http://academic.cleardefinition.com
|
||||||
|
# Iowa State University HCI Graduate Program/VRAC
|
||||||
|
#
|
||||||
|
# Copyright Iowa State University 2009-2010.
|
||||||
|
# Distributed under the Boost Software License, Version 1.0.
|
||||||
|
# (See accompanying file LICENSE_1_0.txt or copy at
|
||||||
|
# http://www.boost.org/LICENSE_1_0.txt)
|
||||||
|
|
||||||
|
if(__get_git_revision_description)
|
||||||
|
return()
|
||||||
|
endif()
|
||||||
|
set(__get_git_revision_description YES)
|
||||||
|
|
||||||
|
# We must run the following at "include" time, not at function call time,
|
||||||
|
# to find the path to this module rather than the path to a calling list file
|
||||||
|
get_filename_component(_gitdescmoddir ${CMAKE_CURRENT_LIST_FILE} PATH)
|
||||||
|
|
||||||
|
function(get_git_head_revision _refspecvar _hashvar)
|
||||||
|
set(GIT_PARENT_DIR "${CMAKE_CURRENT_LIST_DIR}")
|
||||||
|
set(GIT_DIR "${GIT_PARENT_DIR}/.git")
|
||||||
|
while(NOT EXISTS "${GIT_DIR}") # .git dir not found, search parent directories
|
||||||
|
set(GIT_PREVIOUS_PARENT "${GIT_PARENT_DIR}")
|
||||||
|
get_filename_component(GIT_PARENT_DIR ${GIT_PARENT_DIR} PATH)
|
||||||
|
if(GIT_PARENT_DIR STREQUAL GIT_PREVIOUS_PARENT)
|
||||||
|
# We have reached the root directory, we are not in git
|
||||||
|
set(${_refspecvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
|
||||||
|
set(${_hashvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
|
||||||
|
return()
|
||||||
|
endif()
|
||||||
|
set(GIT_DIR "${GIT_PARENT_DIR}/.git")
|
||||||
|
endwhile()
|
||||||
|
# check if this is a submodule
|
||||||
|
if(NOT IS_DIRECTORY ${GIT_DIR})
|
||||||
|
file(READ ${GIT_DIR} submodule)
|
||||||
|
string(REGEX REPLACE "gitdir: (.*)\n$" "\\1" GIT_DIR_RELATIVE ${submodule})
|
||||||
|
get_filename_component(SUBMODULE_DIR ${GIT_DIR} PATH)
|
||||||
|
get_filename_component(GIT_DIR ${SUBMODULE_DIR}/${GIT_DIR_RELATIVE} ABSOLUTE)
|
||||||
|
endif()
|
||||||
|
set(GIT_DATA "${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/git-data")
|
||||||
|
if(NOT EXISTS "${GIT_DATA}")
|
||||||
|
file(MAKE_DIRECTORY "${GIT_DATA}")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
if(NOT EXISTS "${GIT_DIR}/HEAD")
|
||||||
|
return()
|
||||||
|
endif()
|
||||||
|
set(HEAD_FILE "${GIT_DATA}/HEAD")
|
||||||
|
configure_file("${GIT_DIR}/HEAD" "${HEAD_FILE}" COPYONLY)
|
||||||
|
|
||||||
|
configure_file("${_gitdescmoddir}/GetGitRevisionDescription.cmake.in"
|
||||||
|
"${GIT_DATA}/grabRef.cmake"
|
||||||
|
@ONLY)
|
||||||
|
include("${GIT_DATA}/grabRef.cmake")
|
||||||
|
|
||||||
|
set(${_refspecvar} "${HEAD_REF}" PARENT_SCOPE)
|
||||||
|
set(${_hashvar} "${HEAD_HASH}" PARENT_SCOPE)
|
||||||
|
endfunction()
|
||||||
|
|
||||||
|
function(git_describe _var)
|
||||||
|
if(NOT GIT_FOUND)
|
||||||
|
find_package(Git QUIET)
|
||||||
|
endif()
|
||||||
|
get_git_head_revision(refspec hash)
|
||||||
|
if(NOT GIT_FOUND)
|
||||||
|
set(${_var} "GIT-NOTFOUND" PARENT_SCOPE)
|
||||||
|
return()
|
||||||
|
endif()
|
||||||
|
if(NOT hash)
|
||||||
|
set(${_var} "HEAD-HASH-NOTFOUND" PARENT_SCOPE)
|
||||||
|
return()
|
||||||
|
endif()
|
||||||
|
|
||||||
|
# TODO sanitize
|
||||||
|
#if((${ARGN}" MATCHES "&&") OR
|
||||||
|
# (ARGN MATCHES "||") OR
|
||||||
|
# (ARGN MATCHES "\\;"))
|
||||||
|
# message("Please report the following error to the project!")
|
||||||
|
# message(FATAL_ERROR "Looks like someone's doing something nefarious with git_describe! Passed arguments ${ARGN}")
|
||||||
|
#endif()
|
||||||
|
|
||||||
|
#message(STATUS "Arguments to execute_process: ${ARGN}")
|
||||||
|
|
||||||
|
execute_process(COMMAND
|
||||||
|
"${GIT_EXECUTABLE}"
|
||||||
|
describe
|
||||||
|
${hash}
|
||||||
|
${ARGN}
|
||||||
|
WORKING_DIRECTORY
|
||||||
|
"${CMAKE_SOURCE_DIR}"
|
||||||
|
RESULT_VARIABLE
|
||||||
|
res
|
||||||
|
OUTPUT_VARIABLE
|
||||||
|
out
|
||||||
|
ERROR_QUIET
|
||||||
|
OUTPUT_STRIP_TRAILING_WHITESPACE)
|
||||||
|
if(NOT res EQUAL 0)
|
||||||
|
set(out "${out}-${res}-NOTFOUND")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
set(${_var} "${out}" PARENT_SCOPE)
|
||||||
|
endfunction()
|
||||||
|
|
||||||
|
function(git_get_exact_tag _var)
|
||||||
|
git_describe(out --exact-match ${ARGN})
|
||||||
|
set(${_var} "${out}" PARENT_SCOPE)
|
||||||
|
endfunction()
|
|
@ -0,0 +1,41 @@
|
||||||
|
#
|
||||||
|
# Internal file for GetGitRevisionDescription.cmake
|
||||||
|
#
|
||||||
|
# Requires CMake 2.6 or newer (uses the 'function' command)
|
||||||
|
#
|
||||||
|
# Original Author:
|
||||||
|
# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
|
||||||
|
# http://academic.cleardefinition.com
|
||||||
|
# Iowa State University HCI Graduate Program/VRAC
|
||||||
|
#
|
||||||
|
# Copyright Iowa State University 2009-2010.
|
||||||
|
# Distributed under the Boost Software License, Version 1.0.
|
||||||
|
# (See accompanying file LICENSE_1_0.txt or copy at
|
||||||
|
# http://www.boost.org/LICENSE_1_0.txt)
|
||||||
|
|
||||||
|
set(HEAD_HASH)
|
||||||
|
|
||||||
|
file(READ "@HEAD_FILE@" HEAD_CONTENTS LIMIT 1024)
|
||||||
|
|
||||||
|
string(STRIP "${HEAD_CONTENTS}" HEAD_CONTENTS)
|
||||||
|
if(HEAD_CONTENTS MATCHES "ref")
|
||||||
|
# named branch
|
||||||
|
string(REPLACE "ref: " "" HEAD_REF "${HEAD_CONTENTS}")
|
||||||
|
if(EXISTS "@GIT_DIR@/${HEAD_REF}")
|
||||||
|
configure_file("@GIT_DIR@/${HEAD_REF}" "@GIT_DATA@/head-ref" COPYONLY)
|
||||||
|
else()
|
||||||
|
configure_file("@GIT_DIR@/packed-refs" "@GIT_DATA@/packed-refs" COPYONLY)
|
||||||
|
file(READ "@GIT_DATA@/packed-refs" PACKED_REFS)
|
||||||
|
if(${PACKED_REFS} MATCHES "([0-9a-z]*) ${HEAD_REF}")
|
||||||
|
set(HEAD_HASH "${CMAKE_MATCH_1}")
|
||||||
|
endif()
|
||||||
|
endif()
|
||||||
|
else()
|
||||||
|
# detached HEAD
|
||||||
|
configure_file("@GIT_DIR@/HEAD" "@GIT_DATA@/head-ref" COPYONLY)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
if(NOT HEAD_HASH)
|
||||||
|
file(READ "@GIT_DATA@/head-ref" HEAD_HASH LIMIT 1024)
|
||||||
|
string(STRIP "${HEAD_HASH}" HEAD_HASH)
|
||||||
|
endif()
|
|
@ -0,0 +1,44 @@
|
||||||
|
# Create package-config files :
|
||||||
|
# - <projectname>ConfigVersion.cmake
|
||||||
|
# - <projectname>Config.cmake
|
||||||
|
# They are installed in lib/cmake/<projectname>.
|
||||||
|
#
|
||||||
|
# Required variables :
|
||||||
|
# - VERSION
|
||||||
|
# - PROJECT_NAME
|
||||||
|
#
|
||||||
|
|
||||||
|
# Include needed for 'write_basic_package_version_file'
|
||||||
|
include(CMakePackageConfigHelpers)
|
||||||
|
|
||||||
|
write_basic_package_version_file(
|
||||||
|
"${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}ConfigVersion.cmake"
|
||||||
|
VERSION ${VERSION}
|
||||||
|
COMPATIBILITY AnyNewerVersion
|
||||||
|
)
|
||||||
|
|
||||||
|
configure_file(cmake/${PROJECT_NAME}Config.cmake
|
||||||
|
"${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}Config.cmake"
|
||||||
|
COPYONLY
|
||||||
|
)
|
||||||
|
|
||||||
|
# Destination
|
||||||
|
set(config_install_dir lib/cmake/${PROJECT_NAME})
|
||||||
|
|
||||||
|
# Config installation
|
||||||
|
# * <prefix>/lib/cmake/<project>/<project>Targets.cmake
|
||||||
|
install(
|
||||||
|
EXPORT ${PROJECT_NAME}Targets
|
||||||
|
DESTINATION ${config_install_dir}
|
||||||
|
)
|
||||||
|
|
||||||
|
# Config installation
|
||||||
|
# * <prefix>/lib/cmake/<project>/<project>Config.cmake
|
||||||
|
# * <prefix>/lib/cmake/<project>/<project>ConfigVersion.cmake
|
||||||
|
install(
|
||||||
|
FILES
|
||||||
|
cmake/${PROJECT_NAME}Config.cmake
|
||||||
|
"${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}ConfigVersion.cmake"
|
||||||
|
DESTINATION ${config_install_dir}
|
||||||
|
COMPONENT devel
|
||||||
|
)
|
|
@ -0,0 +1,53 @@
|
||||||
|
if(EXISTS "${PROJECT_SOURCE_DIR}/.gitmodules")
|
||||||
|
message(STATUS "Updating submodules to their latest/fixed versions")
|
||||||
|
message(STATUS "(this can take a while, please be patient)")
|
||||||
|
|
||||||
|
### First, get all submodules in
|
||||||
|
if(${GIT_SUBMODULES_CHECKOUT_QUIET})
|
||||||
|
execute_process(
|
||||||
|
COMMAND git submodule update --init --recursive
|
||||||
|
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
|
||||||
|
OUTPUT_QUIET
|
||||||
|
ERROR_QUIET
|
||||||
|
)
|
||||||
|
else()
|
||||||
|
execute_process(
|
||||||
|
COMMAND git submodule update --init --recursive
|
||||||
|
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
|
||||||
|
)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
### Then, checkout each submodule to the specified commit
|
||||||
|
# Note: Execute separate processes here, to make sure each one is run,
|
||||||
|
# should one crash (because of branch not existing, this, that ... whatever)
|
||||||
|
foreach(GIT_SUBMODULE ${GIT_SUBMODULES})
|
||||||
|
|
||||||
|
if( "${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}" STREQUAL "" )
|
||||||
|
message(STATUS "no specific version given for submodule ${GIT_SUBMODULE}, checking out master")
|
||||||
|
set(GIT_SUBMODULE_VERSION_${GIT_SUBMODULE} "master")
|
||||||
|
endif()
|
||||||
|
|
||||||
|
if( "${GIT_SUBMODULE_DIR_${GIT_SUBMODULE}}" STREQUAL "" )
|
||||||
|
set(GIT_SUBMODULES_DIRECTORY external)
|
||||||
|
else()
|
||||||
|
set(GIT_SUBMODULES_DIRECTORY ${GIT_SUBMODULE_DIR_${GIT_SUBMODULE}})
|
||||||
|
endif()
|
||||||
|
|
||||||
|
if(${GIT_SUBMODULES_CHECKOUT_QUIET})
|
||||||
|
execute_process(
|
||||||
|
COMMAND git checkout ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}
|
||||||
|
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}/${GIT_SUBMODULES_DIRECTORY}/${GIT_SUBMODULE}
|
||||||
|
OUTPUT_QUIET
|
||||||
|
ERROR_QUIET
|
||||||
|
)
|
||||||
|
else()
|
||||||
|
message(STATUS "checking out ${GIT_SUBMODULE}'s commit/tag ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}")
|
||||||
|
execute_process(
|
||||||
|
COMMAND git checkout ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}
|
||||||
|
WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}/${GIT_SUBMODULES_DIRECTORY}/${GIT_SUBMODULE}
|
||||||
|
)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
endforeach(${GIT_SUBMODULE})
|
||||||
|
|
||||||
|
endif()
|
|
@ -0,0 +1 @@
|
||||||
|
Subproject commit 8bdb487d2e635db487c81ad745f49edf871369d3
|
|
@ -0,0 +1,31 @@
|
||||||
|
cmake_minimum_required(VERSION 2.8)
|
||||||
|
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake)
|
||||||
|
set(CMAKE_CXX_STANDARD 14)
|
||||||
|
|
||||||
|
# Set the name of your project here
|
||||||
|
project("external")
|
||||||
|
|
||||||
|
include(Common)
|
||||||
|
|
||||||
|
|
||||||
|
include_directories( ${PROJECT_SOURCE_DIR}/external/libGIS ${PROJECT_SOURCE_DIR}/external/easyloggingpp/src )
|
||||||
|
|
||||||
|
FILE(GLOB ElfioHeaders elfio *.hpp)
|
||||||
|
FILE(GLOB GISHeaders libGis *.h)
|
||||||
|
FILE(GLOB LogHeaders easyloggingpp/src *.h)
|
||||||
|
|
||||||
|
set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders} ${LogHeaders})
|
||||||
|
set(LIB_SOURCES
|
||||||
|
libGIS/atmel_generic.c
|
||||||
|
libGIS/ihex.c
|
||||||
|
libGIS/srecord.c
|
||||||
|
easyloggingpp/src/easylogging++.cc
|
||||||
|
)
|
||||||
|
|
||||||
|
# Define two variables in order not to repeat ourselves.
|
||||||
|
set(LIBRARY_NAME external)
|
||||||
|
|
||||||
|
# Define the library
|
||||||
|
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1 @@
|
||||||
|
Subproject commit 850ea2a9f151ed648a989dda1cf44e503e45831f
|
|
@ -0,0 +1 @@
|
||||||
|
Subproject commit fbf8eafc2dab3ac441bc5221d967e23a2e6fdc46
|
|
@ -0,0 +1 @@
|
||||||
|
Subproject commit f82b9dd3018d479230ad68a02da41fa95cad9123
|
|
@ -0,0 +1 @@
|
||||||
|
/src-gen/
|
|
@ -0,0 +1,17 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>riscv</name>
|
||||||
|
<comment></comment>
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
|
||||||
|
</natures>
|
||||||
|
</projectDescription>
|
|
@ -0,0 +1 @@
|
||||||
|
/com.minres.coredsl.CoreDsl.prefs
|
|
@ -0,0 +1,95 @@
|
||||||
|
cmake_minimum_required(VERSION 2.8)
|
||||||
|
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir
|
||||||
|
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir
|
||||||
|
set(CMAKE_CXX_STANDARD 14) # tODO move up to a general cmake config for all sub projects ?
|
||||||
|
|
||||||
|
# CMake useful variables
|
||||||
|
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin")
|
||||||
|
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
|
||||||
|
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
|
||||||
|
|
||||||
|
# Set the name of your project here
|
||||||
|
project("riscv")
|
||||||
|
|
||||||
|
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
|
||||||
|
set(VERSION_MAJOR "0")
|
||||||
|
set(VERSION_MINOR "0")
|
||||||
|
set(VERSION_PATCH "1")
|
||||||
|
set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
|
||||||
|
|
||||||
|
include(Common)
|
||||||
|
|
||||||
|
## Git (and its revision)
|
||||||
|
find_package(Git QUIET) # if we don't find git or FindGit.cmake is not on the system we ignore it.
|
||||||
|
## The Git module will trigger a reconfiguration for each pull that will bring a new revision on the local repository
|
||||||
|
set (VCS_REVISION "-1")
|
||||||
|
if(GIT_FOUND)
|
||||||
|
include(GetGitRevisionDescription)
|
||||||
|
get_git_head_revision(GIT_REFSPEC GIT_SHA1)
|
||||||
|
message(STATUS "GIT branch ${GIT_REFSPEC}")
|
||||||
|
message(STATUS "GIT revision ${GIT_SHA1}")
|
||||||
|
set (VCS_REVISION ${GIT_SHA1})
|
||||||
|
endif()
|
||||||
|
|
||||||
|
# This line finds the boost lib and headers.
|
||||||
|
set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install.
|
||||||
|
find_package(Boost COMPONENTS program_options system thread REQUIRED)
|
||||||
|
|
||||||
|
find_package(LLVM REQUIRED CONFIG)
|
||||||
|
message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
|
||||||
|
message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
|
||||||
|
llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
|
||||||
|
|
||||||
|
find_package(SystemC)
|
||||||
|
if(SystemC_FOUND)
|
||||||
|
add_definitions(-DWITH_SYSTEMC)
|
||||||
|
include_directories(${SystemC_INCLUDE_DIRS})
|
||||||
|
link_directories(${SystemC_LIBRARY_DIRS})
|
||||||
|
else(SystemC_FOUND)
|
||||||
|
message( FATAL_ERROR "SystemC library not found." )
|
||||||
|
endif(SystemC_FOUND)
|
||||||
|
|
||||||
|
if(SCV_FOUND)
|
||||||
|
add_definitions(-DWITH_SCV)
|
||||||
|
link_directories(${SCV_LIBRARY_DIRS})
|
||||||
|
endif(SCV_FOUND)
|
||||||
|
|
||||||
|
# This sets the include directory for the reference project. This is the -I flag in gcc.
|
||||||
|
include_directories(
|
||||||
|
${PROJECT_SOURCE_DIR}/incl
|
||||||
|
${LLVM_INCLUDE_DIRS}
|
||||||
|
)
|
||||||
|
|
||||||
|
add_dependent_subproject(dbt-core)
|
||||||
|
add_dependent_subproject(sc-components)
|
||||||
|
add_dependent_header(util)
|
||||||
|
|
||||||
|
include_directories(
|
||||||
|
${PROJECT_SOURCE_DIR}/incl
|
||||||
|
${PROJECT_SOURCE_DIR}/../external/elfio
|
||||||
|
${PROJECT_SOURCE_DIR}/../external/libGIS
|
||||||
|
${PROJECT_SOURCE_DIR}/../external/easyloggingpp/src
|
||||||
|
${Boost_INCLUDE_DIRS}
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
|
||||||
|
set(CMAKE_MACOSX_RPATH ON)
|
||||||
|
set(CMAKE_SKIP_BUILD_RPATH FALSE)
|
||||||
|
set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
|
||||||
|
set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
|
||||||
|
set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
|
||||||
|
|
||||||
|
add_subdirectory(src)
|
||||||
|
|
||||||
|
#
|
||||||
|
# SYSTEM PACKAGING (RPM, TGZ, ...)
|
||||||
|
# _____________________________________________________________________________
|
||||||
|
|
||||||
|
#include(CPackConfig)
|
||||||
|
|
||||||
|
#
|
||||||
|
# CMAKE PACKAGING (for other CMake projects to use this one easily)
|
||||||
|
# _____________________________________________________________________________
|
||||||
|
|
||||||
|
#include(PackageConfigurator)
|
|
@ -0,0 +1,168 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Contributors:
|
||||||
|
* eyck@minres.com - initial API and implementation
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _CLI_OPTIONS_H_
|
||||||
|
#define _CLI_OPTIONS_H_
|
||||||
|
#include <boost/program_options.hpp>
|
||||||
|
#include <easylogging++.h>
|
||||||
|
|
||||||
|
namespace {
|
||||||
|
const size_t ERROR_IN_COMMAND_LINE = 1;
|
||||||
|
const size_t SUCCESS = 0;
|
||||||
|
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
|
||||||
|
|
||||||
|
|
||||||
|
inline void enable_log_level(el::Configurations& conf, int level){
|
||||||
|
switch(level){
|
||||||
|
case 0:
|
||||||
|
conf.set(el::Level::Fatal, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
case 1:
|
||||||
|
conf.set(el::Level::Error, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
case 2:
|
||||||
|
conf.set(el::Level::Warning, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
case 3:
|
||||||
|
conf.set(el::Level::Info, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
case 4:
|
||||||
|
conf.set(el::Level::Debug, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
case 5:
|
||||||
|
conf.set(el::Level::Trace, el::ConfigurationType::Enabled, "false");
|
||||||
|
/* no break */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
inline void configure_default_logger(boost::program_options::variables_map& vm){
|
||||||
|
el::Configurations defaultConf;
|
||||||
|
defaultConf.setToDefault();
|
||||||
|
defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||||
|
defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||||
|
defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||||
|
defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||||
|
defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
|
||||||
|
if(vm.count("verbose"))
|
||||||
|
enable_log_level(defaultConf, vm["verbose"].as<int>());
|
||||||
|
if(vm.count("log-file"))
|
||||||
|
defaultConf.set(el::Level::Global,el::ConfigurationType::Filename, vm["log-file"].as<std::string>());
|
||||||
|
// default logger uses default configurations
|
||||||
|
el::Loggers::reconfigureLogger("default", defaultConf);
|
||||||
|
}
|
||||||
|
|
||||||
|
inline void configure_debugger_logger() {
|
||||||
|
// configure the connection logger
|
||||||
|
el::Logger* gdbServerLogger = el::Loggers::getLogger("connection");
|
||||||
|
el::Configurations gdbServerConf;
|
||||||
|
gdbServerConf.setToDefault();
|
||||||
|
gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||||
|
gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||||
|
gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||||
|
gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||||
|
gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} %level [%logger] %msg");
|
||||||
|
enable_log_level(gdbServerConf, 5);
|
||||||
|
gdbServerLogger->configure(gdbServerConf);
|
||||||
|
}
|
||||||
|
|
||||||
|
inline void configure_disass_logger(boost::program_options::variables_map& vm) {
|
||||||
|
el::Logger* disassLogger = el::Loggers::getLogger("disass");
|
||||||
|
el::Configurations disassConf;
|
||||||
|
if(vm.count("disass")){
|
||||||
|
auto file_name=vm["disass"].as<std::string>();
|
||||||
|
disassConf.setToDefault();
|
||||||
|
if (file_name.length() > 0) {
|
||||||
|
disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
|
||||||
|
std::string("true"));
|
||||||
|
disassConf.set(el::Level::Global,
|
||||||
|
el::ConfigurationType::ToStandardOutput, std::string("false"));
|
||||||
|
disassConf.set(el::Level::Global, el::ConfigurationType::Format,
|
||||||
|
std::string("%msg"));
|
||||||
|
disassConf.set(el::Level::Global, el::ConfigurationType::Filename,
|
||||||
|
file_name);
|
||||||
|
std::ofstream str(file_name); // just to clear the file
|
||||||
|
} else {
|
||||||
|
disassConf.set(el::Level::Global, el::ConfigurationType::Format,
|
||||||
|
"%datetime{%H:%m:%s.%g} [%logger] %msg");
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
enable_log_level(disassConf, 0);
|
||||||
|
}
|
||||||
|
disassLogger->configure(disassConf);
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace
|
||||||
|
|
||||||
|
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){
|
||||||
|
namespace po = boost::program_options;
|
||||||
|
po::options_description desc("Options");
|
||||||
|
desc.add_options()
|
||||||
|
("help,h", "Print help message")
|
||||||
|
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
|
||||||
|
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged")
|
||||||
|
("logging-flags", po::value<int>(),"Sets logging flag(s).")
|
||||||
|
("log-file", po::value<std::string>(),"Sets default log file.")
|
||||||
|
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly")
|
||||||
|
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load")
|
||||||
|
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")
|
||||||
|
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
|
||||||
|
("dump-ir", "dump the intermediate representation")
|
||||||
|
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
|
||||||
|
("systemc,s", "Run as SystemC simulation")
|
||||||
|
("time", po::value<int>(), "SystemC siimulation time in ms")
|
||||||
|
("reset,r", po::value<std::string>(), "reset address")
|
||||||
|
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\
|
||||||
|
("mem,m", po::value<std::string>(), "the memory input file");
|
||||||
|
try {
|
||||||
|
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
|
||||||
|
// --help option
|
||||||
|
if ( vm.count("help") ){
|
||||||
|
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
po::notify(vm); // throws on error, so do after help in case
|
||||||
|
} catch(po::error& e){
|
||||||
|
// there are problems
|
||||||
|
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||||
|
std::cerr << desc << std::endl;
|
||||||
|
return ERROR_IN_COMMAND_LINE;
|
||||||
|
}
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
#endif /* _CLI_OPTIONS_H_ */
|
|
@ -0,0 +1,200 @@
|
||||||
|
/*******************************************************************************
|
||||||
|
* Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Contributors:
|
||||||
|
* eyck@minres.com - initial API and implementation
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _MINRV_IMA_H_
|
||||||
|
#define _MINRV_IMA_H_
|
||||||
|
|
||||||
|
#include <iss/arch_if.h>
|
||||||
|
#include <iss/vm_if.h>
|
||||||
|
#include <iss/arch/traits.h>
|
||||||
|
|
||||||
|
namespace iss {
|
||||||
|
namespace arch {
|
||||||
|
|
||||||
|
struct minrv_ima;
|
||||||
|
|
||||||
|
template<>
|
||||||
|
struct traits<minrv_ima> {
|
||||||
|
|
||||||
|
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
|
||||||
|
|
||||||
|
enum reg_e {
|
||||||
|
X0,
|
||||||
|
X1,
|
||||||
|
X2,
|
||||||
|
X3,
|
||||||
|
X4,
|
||||||
|
X5,
|
||||||
|
X6,
|
||||||
|
X7,
|
||||||
|
X8,
|
||||||
|
X9,
|
||||||
|
X10,
|
||||||
|
X11,
|
||||||
|
X12,
|
||||||
|
X13,
|
||||||
|
X14,
|
||||||
|
X15,
|
||||||
|
X16,
|
||||||
|
X17,
|
||||||
|
X18,
|
||||||
|
X19,
|
||||||
|
X20,
|
||||||
|
X21,
|
||||||
|
X22,
|
||||||
|
X23,
|
||||||
|
X24,
|
||||||
|
X25,
|
||||||
|
X26,
|
||||||
|
X27,
|
||||||
|
X28,
|
||||||
|
X29,
|
||||||
|
X30,
|
||||||
|
X31,
|
||||||
|
PC,
|
||||||
|
NUM_REGS,
|
||||||
|
NEXT_PC=NUM_REGS,
|
||||||
|
TRAP_STATE,
|
||||||
|
PENDING_TRAP,
|
||||||
|
MACHINE_STATE,
|
||||||
|
ICOUNT
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef uint32_t reg_t;
|
||||||
|
|
||||||
|
typedef uint32_t addr_t;
|
||||||
|
|
||||||
|
typedef uint32_t code_word_t; //TODO: check removal
|
||||||
|
|
||||||
|
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
|
||||||
|
|
||||||
|
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
|
||||||
|
|
||||||
|
constexpr static unsigned reg_bit_width(unsigned r) {
|
||||||
|
const uint32_t MinRV_IMA_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
|
||||||
|
return MinRV_IMA_reg_size[r];
|
||||||
|
}
|
||||||
|
|
||||||
|
constexpr static unsigned reg_byte_offset(unsigned r) {
|
||||||
|
const uint32_t MinRV_IMA_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
|
||||||
|
return MinRV_IMA_reg_byte_offset[r];
|
||||||
|
}
|
||||||
|
|
||||||
|
enum sreg_flag_e {FLAGS};
|
||||||
|
|
||||||
|
enum mem_type_e {MEM,CSR,FENCE,RES};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
struct minrv_ima: public arch_if {
|
||||||
|
|
||||||
|
using virt_addr_t = typename traits<minrv_ima>::virt_addr_t;
|
||||||
|
using phys_addr_t = typename traits<minrv_ima>::phys_addr_t;
|
||||||
|
using reg_t = typename traits<minrv_ima>::reg_t;
|
||||||
|
using addr_t = typename traits<minrv_ima>::addr_t;
|
||||||
|
|
||||||
|
minrv_ima();
|
||||||
|
~minrv_ima();
|
||||||
|
|
||||||
|
void reset(uint64_t address=0);
|
||||||
|
|
||||||
|
// virtual void loadFile(std::string name, int type=-1);
|
||||||
|
|
||||||
|
uint8_t* get_regs_base_ptr() override;
|
||||||
|
|
||||||
|
void get_reg(short idx, std::vector<uint8_t>& value) override;
|
||||||
|
void set_reg(short idx, const std::vector<uint8_t>& value) override;
|
||||||
|
|
||||||
|
bool get_flag(int flag) override;
|
||||||
|
void set_flag(int, bool value) override;
|
||||||
|
|
||||||
|
void update_flags(operations op, uint64_t opr1, uint64_t opr2) override;
|
||||||
|
|
||||||
|
void notify_phase(exec_phase phase){
|
||||||
|
if(phase==ISTART){
|
||||||
|
++reg.icount;
|
||||||
|
reg.PC=reg.NEXT_PC;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint64_t get_icount() { return reg.icount;}
|
||||||
|
|
||||||
|
virtual phys_addr_t v2p(const iss::addr_t& pc);
|
||||||
|
|
||||||
|
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
|
||||||
|
|
||||||
|
protected:
|
||||||
|
struct MinRV_IMA_regs {
|
||||||
|
uint32_t X0;
|
||||||
|
uint32_t X1;
|
||||||
|
uint32_t X2;
|
||||||
|
uint32_t X3;
|
||||||
|
uint32_t X4;
|
||||||
|
uint32_t X5;
|
||||||
|
uint32_t X6;
|
||||||
|
uint32_t X7;
|
||||||
|
uint32_t X8;
|
||||||
|
uint32_t X9;
|
||||||
|
uint32_t X10;
|
||||||
|
uint32_t X11;
|
||||||
|
uint32_t X12;
|
||||||
|
uint32_t X13;
|
||||||
|
uint32_t X14;
|
||||||
|
uint32_t X15;
|
||||||
|
uint32_t X16;
|
||||||
|
uint32_t X17;
|
||||||
|
uint32_t X18;
|
||||||
|
uint32_t X19;
|
||||||
|
uint32_t X20;
|
||||||
|
uint32_t X21;
|
||||||
|
uint32_t X22;
|
||||||
|
uint32_t X23;
|
||||||
|
uint32_t X24;
|
||||||
|
uint32_t X25;
|
||||||
|
uint32_t X26;
|
||||||
|
uint32_t X27;
|
||||||
|
uint32_t X28;
|
||||||
|
uint32_t X29;
|
||||||
|
uint32_t X30;
|
||||||
|
uint32_t X31;
|
||||||
|
uint32_t PC;
|
||||||
|
uint32_t NEXT_PC;
|
||||||
|
uint32_t trap_state, pending_trap, machine_state;
|
||||||
|
uint64_t icount;
|
||||||
|
} reg;
|
||||||
|
};
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* _MINRV_IMA_H_ */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,56 @@
|
||||||
|
# library files
|
||||||
|
FILE(GLOB RiscVHeaders *.h)
|
||||||
|
set(LIB_HEADERS ${RiscVHeaders} )
|
||||||
|
set(LIB_SOURCES
|
||||||
|
iss/minrv_ima.cpp
|
||||||
|
internal/vm_minrv_ima.cpp
|
||||||
|
)
|
||||||
|
|
||||||
|
set(APP_HEADERS )
|
||||||
|
|
||||||
|
set(APP_SOURCES main.cpp)
|
||||||
|
|
||||||
|
# Define two variables in order not to repeat ourselves.
|
||||||
|
set(LIBRARY_NAME riscv)
|
||||||
|
|
||||||
|
# Define the library
|
||||||
|
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
|
||||||
|
|
||||||
|
set_target_properties(${LIBRARY_NAME} PROPERTIES
|
||||||
|
VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists.
|
||||||
|
FRAMEWORK FALSE
|
||||||
|
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
|
||||||
|
)
|
||||||
|
|
||||||
|
# This is a make target, so you can do a "make riscv-sc"
|
||||||
|
set(APPLICATION_NAME riscv-sc)
|
||||||
|
|
||||||
|
add_executable(${APPLICATION_NAME} ${APP_SOURCES})
|
||||||
|
|
||||||
|
# Links the target exe against the libraries
|
||||||
|
target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
|
||||||
|
target_link_libraries(${APPLICATION_NAME} dbt-core)
|
||||||
|
target_link_libraries(${APPLICATION_NAME} sc-components)
|
||||||
|
target_link_libraries(${APPLICATION_NAME} external)
|
||||||
|
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
|
||||||
|
#target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
|
||||||
|
#if(SCV_FOUND)
|
||||||
|
#target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
|
||||||
|
#endif(SCV_FOUND)
|
||||||
|
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
|
||||||
|
|
||||||
|
# Says how and where to install software
|
||||||
|
# Targets:
|
||||||
|
# * <prefix>/lib/<libraries>
|
||||||
|
# * header location after install: <prefix>/include/<project>/*.h
|
||||||
|
# * headers can be included by C++ code `#<project>/Bar.hpp>`
|
||||||
|
install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME}
|
||||||
|
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
|
||||||
|
ARCHIVE DESTINATION lib COMPONENT libs # static lib
|
||||||
|
RUNTIME DESTINATION bin COMPONENT libs # binaries
|
||||||
|
LIBRARY DESTINATION lib COMPONENT libs # shared lib
|
||||||
|
FRAMEWORK DESTINATION bin COMPONENT libs # for mac
|
||||||
|
PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package)
|
||||||
|
INCLUDES DESTINATION incl # headers
|
||||||
|
)
|
||||||
|
|
|
@ -0,0 +1,108 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV32A extends RV32IBase{
|
||||||
|
|
||||||
|
address_spaces {
|
||||||
|
RES[8]
|
||||||
|
}
|
||||||
|
|
||||||
|
instructions{
|
||||||
|
LR.W {
|
||||||
|
encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d";
|
||||||
|
if(rd!=0){
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
X[rd]<= sext(MEM[offs]{32}, XLEN);
|
||||||
|
RES[offs]{32}<=sext(-1, 32);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SC.W {
|
||||||
|
encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res1[32] <= RES[offs]{32};
|
||||||
|
if(res1!=0)
|
||||||
|
MEM[offs]{32} <= X[rs2];
|
||||||
|
if(rd!=0) X[rd]<= choose(res1!=0, 0, 1);
|
||||||
|
}
|
||||||
|
AMOSWAP.W{
|
||||||
|
encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
if(rd!=0) X[rd]<=sext(MEM[offs]{32});
|
||||||
|
MEM[offs]{32}<=X[rs2];
|
||||||
|
}
|
||||||
|
AMOADD.W{
|
||||||
|
encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<=res1 + X[rs2];
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOXOR.W{
|
||||||
|
encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<=res1 ^ X[rs2];
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOAND.W{
|
||||||
|
encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN] <=res1 & X[rs2];
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOOR.W {
|
||||||
|
encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<=res1 | X[rs2];
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOMIN.W{
|
||||||
|
encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<= choose(res1's>X[rs2]s, X[rs2], res1);
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOMAX.W{
|
||||||
|
encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= sext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOMINU.W{
|
||||||
|
encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= zext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
AMOMAXU.W{
|
||||||
|
encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
|
||||||
|
val offs[XLEN]<=X[rs1];
|
||||||
|
val res1[XLEN] <= zext(MEM[offs]{32});
|
||||||
|
if(rd!=0) X[rd]<=res1;
|
||||||
|
val res2[XLEN]<= choose(res1'u<X[rs2]'u, X[rs2], res1);
|
||||||
|
MEM[offs]{32}<=res2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,310 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV32CI {
|
||||||
|
constants {
|
||||||
|
XLEN
|
||||||
|
}
|
||||||
|
address_spaces {
|
||||||
|
MEM[8]
|
||||||
|
}
|
||||||
|
registers {
|
||||||
|
[31:0] X[XLEN],
|
||||||
|
PC[XLEN](is_pc)
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
C.ADDI4SPN { //(RES, nzuimm=0)
|
||||||
|
encoding: b000 | nzuimm[5:4] | nzuimm[9:6] | nzuimm[2:2] | nzuimm[3:3] | rd[2:0] | b00;
|
||||||
|
args_disass: "x%rd$d, 0x%nzuimm$05x";
|
||||||
|
if(nzuimm == 0)
|
||||||
|
raise(0, 2);
|
||||||
|
val rd_idx[5] <= rd+8;
|
||||||
|
val x2_idx[5] <= 2;
|
||||||
|
X[rd_idx] <= X[x2_idx] + nzuimm;
|
||||||
|
}
|
||||||
|
C.LW { // (RV32)
|
||||||
|
encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
|
||||||
|
args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x";
|
||||||
|
val rs1_idx[5] <= rs1+8;
|
||||||
|
val adr[XLEN] <= X[rs1_idx]+uimm;
|
||||||
|
val rd_idx[5] <= rd+8;
|
||||||
|
X[rd_idx] <= MEM[adr]{32};
|
||||||
|
}
|
||||||
|
C.SW {//(RV32)
|
||||||
|
encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
|
||||||
|
args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x";
|
||||||
|
val rs1_idx[5] <= rs1+8;
|
||||||
|
val adr[XLEN] <= X[rs1_idx]+uimm;
|
||||||
|
val rs2_idx[5] <= rs2+8;
|
||||||
|
MEM[adr]{32} <= X[rs2_idx];
|
||||||
|
}
|
||||||
|
C.NOP {//(RV32)
|
||||||
|
encoding: b000 | b0 | b00000 | b00000 | b01; //TODO
|
||||||
|
args_disass: "";
|
||||||
|
}
|
||||||
|
C.ADDI {//(RV32)
|
||||||
|
encoding:b000 | nzimm[5:5]s | rs1[4:0] | nzimm[4:0]s | b01;
|
||||||
|
args_disass: "x%rs1$d, 0x%nzimm$05x";
|
||||||
|
if(nzimm == 0)
|
||||||
|
raise(0, 2);
|
||||||
|
X[rs1] <= X[rs1] + nzimm;
|
||||||
|
|
||||||
|
}
|
||||||
|
// C.JAL will be overwritten by C.ADDIW for RV64/128
|
||||||
|
C.JAL(no_cont) {//(RV32)
|
||||||
|
encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
|
||||||
|
args_disass: "0x%imm$05x";
|
||||||
|
val rd[5] <= 1;
|
||||||
|
X[rd] <= PC+2;
|
||||||
|
PC<=PC+imm;
|
||||||
|
}
|
||||||
|
C.LI {//(RV32)
|
||||||
|
encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
|
||||||
|
args_disass: "x%rd$d, 0x%imm$05x";
|
||||||
|
if(rd == 0) raise(0, 2);
|
||||||
|
X[rd] <= imm;
|
||||||
|
}
|
||||||
|
// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
|
||||||
|
C.LUI {//(RV32)
|
||||||
|
encoding:b011 | nzimm[17:17]s | rd[4:0] | nzimm[16:12]s | b01;
|
||||||
|
args_disass: "x%rd$d, 0x%nzimm$05x";
|
||||||
|
if(rd == 0) raise(0, 2);
|
||||||
|
if(rd == 2) raise(0, 2);
|
||||||
|
if(nzimm == 0) raise(0, 2);
|
||||||
|
X[rd] <= nzimm;
|
||||||
|
}
|
||||||
|
C.ADDI16SP {//(RV32)
|
||||||
|
encoding:b011 | nzimm[9:9]s | b00010 | nzimm[4:4]s |nzimm[6:6]s | nzimm[8:7]s | nzimm[5:5]s | b01;
|
||||||
|
args_disass: "0x%nzimm$05x";
|
||||||
|
val x2_idx[5] <= 2;
|
||||||
|
X[x2_idx] <= X[x2_idx]s + nzimm;
|
||||||
|
}
|
||||||
|
C.SRLI {//(RV32 nse)
|
||||||
|
encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
|
||||||
|
args_disass: "x(8+%rs1$d), %shamt$d";
|
||||||
|
if(shamt > 31) raise(0, 2);
|
||||||
|
val rs1_idx[5] <= rs1+8;
|
||||||
|
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
|
||||||
|
}
|
||||||
|
C.SRAI {//(RV32)
|
||||||
|
encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
|
||||||
|
args_disass: "x(8+%rs1$d), %shamt$d";
|
||||||
|
if(shamt > 31) raise(0, 2);
|
||||||
|
val rs1_idx[5] <= rs1+8;
|
||||||
|
X[rs1_idx] <= shra(X[rs1_idx], shamt);
|
||||||
|
}
|
||||||
|
C.ANDI {//(RV32)
|
||||||
|
encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
|
||||||
|
args_disass: "x(8+%rs1$d), 0x%imm$05x";
|
||||||
|
val rs1_idx[5] <= rs1 + 8;
|
||||||
|
X[rs1_idx] <= X[rs1_idx] & imm;
|
||||||
|
}
|
||||||
|
C.SUB {//(RV32)
|
||||||
|
encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x(8+%rd$d), x(8+%rs2$d)";
|
||||||
|
val rd_idx[5] <= rd + 8;
|
||||||
|
val rs2_idx[5] <= rs2 + 8;
|
||||||
|
X[rd_idx] <= X[rd_idx] - X[rs2_idx];
|
||||||
|
}
|
||||||
|
C.XOR {//(RV32)
|
||||||
|
encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x(8+%rd$d), x(8+%rs2$d)";
|
||||||
|
val rd_idx[5] <= rd + 8;
|
||||||
|
val rs2_idx[5] <= rs2 + 8;
|
||||||
|
X[rd_idx] <= X[rd_idx] ^ X[rs2_idx];
|
||||||
|
}
|
||||||
|
C.OR {//(RV32)
|
||||||
|
encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x(8+%rd$d), x(8+%rs2$d)";
|
||||||
|
val rd_idx[5] <= rd + 8;
|
||||||
|
val rs2_idx[5] <= rs2 + 8;
|
||||||
|
X[rd_idx] <= X[rd_idx] | X[rs2_idx];
|
||||||
|
}
|
||||||
|
C.AND {//(RV32)
|
||||||
|
encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x(8+%rd$d), x(8+%rs2$d)";
|
||||||
|
val rd_idx[5] <= rd + 8;
|
||||||
|
val rs2_idx[5] <= rs2 + 8;
|
||||||
|
X[rd_idx] <= X[rd_idx] & X[rs2_idx];
|
||||||
|
}
|
||||||
|
C.J(no_cont) {//(RV32)
|
||||||
|
encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
|
||||||
|
args_disass: "0x%imm$05x";
|
||||||
|
PC<=PC+imm;
|
||||||
|
}
|
||||||
|
C.BEQZ(no_cont) {//(RV32)
|
||||||
|
encoding:b110 | imm[8:8]s | imm[4:3]s | rs1d[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
|
||||||
|
args_disass: "x(8+%rs1d$d), 0x%imm$05x";
|
||||||
|
val rs1[5] <= rs1d+8;
|
||||||
|
PC<=choose(X[rs1]==0, PC+imm, PC+2);
|
||||||
|
}
|
||||||
|
C.BNEZ(no_cont) {//(RV32)
|
||||||
|
encoding:b111 | imm[8:8] | imm[4:3] | rs1d[2:0] | imm[7:6] | imm[2:1] | imm[5:5] | b01;
|
||||||
|
args_disass: "x(8+%rs1d$d),, 0x%imm$05x";
|
||||||
|
val rs1[5] <= rs1d+8;
|
||||||
|
PC<=choose(X[rs1]!=0, PC+imm, PC+2);
|
||||||
|
}
|
||||||
|
C.SLLI {//(RV32)
|
||||||
|
encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
|
||||||
|
args_disass: "x%rs1$d, %shamt$d";
|
||||||
|
if(rs1 == 0) raise(0, 2);
|
||||||
|
if(shamt > 31) raise(0, 2);
|
||||||
|
X[rs1] <= shll(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
C.LQSP {//(RV128)
|
||||||
|
encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:4] | uimm[9:6] | b10;
|
||||||
|
}
|
||||||
|
C.LWSP {//
|
||||||
|
encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
|
||||||
|
args_disass: "x%rd$d, sp, 0x%uimm$05x";
|
||||||
|
val x2_idx[5] <= 2;
|
||||||
|
val offs[XLEN] <= X[x2_idx] + uimm;
|
||||||
|
X[rd] <= MEM[offs]{32};
|
||||||
|
}
|
||||||
|
// order matters as C.JR is a special case of C.JR
|
||||||
|
C.MV {//(RV32)
|
||||||
|
encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
|
||||||
|
args_disass: "x%rd$d, x%rs2$d";
|
||||||
|
X[rd] <= X[rs2];
|
||||||
|
}
|
||||||
|
C.JR(no_cont) {//(RV32)
|
||||||
|
encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
|
||||||
|
args_disass: "x%rs1$d";
|
||||||
|
PC <= X[rs1];
|
||||||
|
}
|
||||||
|
C.EBREAK(no_cont) {//(RV32)
|
||||||
|
encoding:b100 | b1 | b00000 | b00000 | b10;
|
||||||
|
raise(0, 3);
|
||||||
|
}
|
||||||
|
// order matters as C.JALR is a special case of C.ADD
|
||||||
|
C.ADD {//(RV32)
|
||||||
|
encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
|
||||||
|
args_disass: "x%rd$d, x%rs2$d";
|
||||||
|
X[rd] <= X[rd] + X[rs2];
|
||||||
|
}
|
||||||
|
C.JALR(no_cont) {//(RV32)
|
||||||
|
encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
|
||||||
|
args_disass: "x%rs1$d";
|
||||||
|
val rd[5] <= 1;
|
||||||
|
X[rd] <= PC+2;
|
||||||
|
PC<=X[rs1];
|
||||||
|
}
|
||||||
|
C.SWSP {//
|
||||||
|
encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
|
||||||
|
args_disass: "x2+0x%uimm$05x, x%rs2$d";
|
||||||
|
val x2_idx[5] <= 2;
|
||||||
|
val offs[XLEN] <= X[x2_idx] + uimm;
|
||||||
|
MEM[offs]{32} <= X[rs2];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
InsructionSet RV32CF extends RV32CI {
|
||||||
|
constants {
|
||||||
|
XLEN, FLEN
|
||||||
|
}
|
||||||
|
address_spaces {
|
||||||
|
MEM[8]
|
||||||
|
}
|
||||||
|
registers {
|
||||||
|
[31:0] X[XLEN],
|
||||||
|
[31:0] F[FLEN]
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
C.FLD { //(RV32/64)
|
||||||
|
encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.FLW {//(RV32)
|
||||||
|
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.FSD { //(RV32/64)
|
||||||
|
encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.FSW {//(RV32)
|
||||||
|
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.FLDSP {//(RV32/64)
|
||||||
|
encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
|
||||||
|
}
|
||||||
|
C.FLWSP {//RV32
|
||||||
|
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
|
||||||
|
}
|
||||||
|
C.FSDSP {//(RV32/64)
|
||||||
|
encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
|
||||||
|
}
|
||||||
|
C.FSWSP {//(RV32)
|
||||||
|
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
InsructionSet RV64CI extends RV32CI {
|
||||||
|
constants {
|
||||||
|
XLEN
|
||||||
|
}
|
||||||
|
address_spaces {
|
||||||
|
MEM[8]
|
||||||
|
}
|
||||||
|
registers {
|
||||||
|
[31:0] X[XLEN],
|
||||||
|
PC[XLEN](is_pc)
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
C.LD {//(RV64/128)
|
||||||
|
encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.SD { //(RV64/128)
|
||||||
|
encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.SUBW {//(RV64/128, RV32 res)
|
||||||
|
encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x%rd$d, sp, 0x%imm$05x";
|
||||||
|
}
|
||||||
|
C.ADDW {//(RV64/128 RV32 res)
|
||||||
|
encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
|
||||||
|
args_disass: "x%rd$d, sp, 0x%imm$05x";
|
||||||
|
}
|
||||||
|
C.ADDIW {//(RV64/128)
|
||||||
|
encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01;
|
||||||
|
}
|
||||||
|
C.SRLI64 {//(RV32/64/128)
|
||||||
|
encoding:b100 | b0 | b00 | rs1[2:0] | b00000 | b01;
|
||||||
|
}
|
||||||
|
C.SRAI64 {//(RV32/64/128)
|
||||||
|
encoding:b100 | b0 | b01 | rs1[2:0] | b00000 | b01;
|
||||||
|
}
|
||||||
|
C.SLLI64 {//(RV128 RV32/64)
|
||||||
|
encoding:b000 | b0 | rs1[4:0] | b00000 | b10;
|
||||||
|
}
|
||||||
|
C.LDSP {//(RV64/128
|
||||||
|
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
|
||||||
|
args_disass: "x%rd$d, sp, 0x%imm$05x";
|
||||||
|
}
|
||||||
|
C.SDSP {//(RV64/128)
|
||||||
|
encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
InsructionSet RV128CI extends RV64CI {
|
||||||
|
constants {
|
||||||
|
XLEN
|
||||||
|
}
|
||||||
|
address_spaces {
|
||||||
|
MEM[8]
|
||||||
|
}
|
||||||
|
registers {
|
||||||
|
[31:0] X[XLEN],
|
||||||
|
PC[XLEN](is_pc)
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
C.LQ { //(RV128)
|
||||||
|
encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.SQ { //(RV128)
|
||||||
|
encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
|
||||||
|
}
|
||||||
|
C.SQSP {//(RV128)
|
||||||
|
encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,105 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV32F extends RV32IBase{
|
||||||
|
constants {
|
||||||
|
FLEN, fcsr
|
||||||
|
}
|
||||||
|
registers {
|
||||||
|
[31:0] F[FLEN]
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
FLW {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
F[rd]<=MEM[offs];
|
||||||
|
}
|
||||||
|
FSW {
|
||||||
|
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
MEM[offs]<=F[rs2];
|
||||||
|
}
|
||||||
|
FMADD.S {
|
||||||
|
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
|
||||||
|
F[rd]f<= F[rs1]f * F[rs2]f * F[rs3]f;
|
||||||
|
}
|
||||||
|
FMSUB.S {
|
||||||
|
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
|
||||||
|
F[rd]f<=F[rs1]f * F[rs2]f -F[rs3]f;
|
||||||
|
}
|
||||||
|
FNMSUB.S {
|
||||||
|
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
|
||||||
|
F[rd]f<=-F[rs1]f * F[rs2]f- F[rs3]f;
|
||||||
|
}
|
||||||
|
FNMADD.S {
|
||||||
|
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
|
||||||
|
F[rd]f<=-F[rs1]f*F[rs2]f+F[rs3]f;
|
||||||
|
}
|
||||||
|
FADD.S {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
F[rd]f <= F[rs1]f + F[rs2]f;
|
||||||
|
}
|
||||||
|
FSUB.S {
|
||||||
|
encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
F[rd]f <= F[rs1]f - F[rs2]f;
|
||||||
|
}
|
||||||
|
FMUL.S {
|
||||||
|
encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
F[rd]f <= F[rs1]f * F[rs2];
|
||||||
|
}
|
||||||
|
FDIV.S {
|
||||||
|
encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
F[rd]f <= F[rs1]f / F[rs2]f;
|
||||||
|
}
|
||||||
|
FSQRT.S {
|
||||||
|
encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
F[rd]f<=sqrt(F[rs1]f);
|
||||||
|
}
|
||||||
|
FSGNJ.S {
|
||||||
|
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FSGNJN.S {
|
||||||
|
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FSGNJX.S {
|
||||||
|
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FMIN.S {
|
||||||
|
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||||
|
F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
|
||||||
|
}
|
||||||
|
FMAX.S {
|
||||||
|
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
|
||||||
|
F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
|
||||||
|
}
|
||||||
|
FCVT.W.S {
|
||||||
|
encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FCVT.WU.S {
|
||||||
|
encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FMV.X.W {
|
||||||
|
encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FEQ.S {
|
||||||
|
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FLT.S {
|
||||||
|
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FLE.S {
|
||||||
|
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FCLASS.S {
|
||||||
|
encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FCVT.S.W {
|
||||||
|
encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FCVT.S.WU {
|
||||||
|
encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
FMV.W.X {
|
||||||
|
encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,308 @@
|
||||||
|
InsructionSet RV32IBase {
|
||||||
|
constants {
|
||||||
|
XLEN,
|
||||||
|
XLEN_BIT_MASK,
|
||||||
|
PCLEN,
|
||||||
|
fence,
|
||||||
|
fencei,
|
||||||
|
fencevmal,
|
||||||
|
fencevmau
|
||||||
|
}
|
||||||
|
|
||||||
|
address_spaces {
|
||||||
|
MEM[8], CSR[XLEN], FENCE[XLEN]
|
||||||
|
}
|
||||||
|
|
||||||
|
registers {
|
||||||
|
[31:0] X[XLEN],
|
||||||
|
PC[XLEN](is_pc)
|
||||||
|
}
|
||||||
|
|
||||||
|
instructions {
|
||||||
|
LUI{
|
||||||
|
encoding: imm[31:12]s | rd[4:0] | b0110111;
|
||||||
|
args_disass: "x%rd$d, 0x%imm$05x";
|
||||||
|
if(rd!=0) X[rd] <= imm;
|
||||||
|
}
|
||||||
|
AUIPC{
|
||||||
|
encoding: imm[31:12]s | rd[4:0] | b0010111;
|
||||||
|
args_disass: "x%rd%, 0x%imm$08x";
|
||||||
|
if(rd!=0) X[rd] <= PC+imm;
|
||||||
|
}
|
||||||
|
JAL(no_cont){
|
||||||
|
encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
|
||||||
|
args_disass: "x%rd$d, 0x%imm$x";
|
||||||
|
if(rd!=0) X[rd] <= PC+4;
|
||||||
|
PC<=PC+imm;
|
||||||
|
}
|
||||||
|
JALR(no_cont){
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
|
||||||
|
if(rd!=0) X[rd] <= PC+4;
|
||||||
|
val ret[XLEN] <= X[rs1]+ imm;
|
||||||
|
PC<=ret& ~0x1;
|
||||||
|
}
|
||||||
|
BEQ(no_cont){
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
BNE(no_cont){
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
BLT(no_cont){
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
BGE(no_cont) {
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
BLTU(no_cont) {
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
BGEU(no_cont) {
|
||||||
|
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
|
||||||
|
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
|
||||||
|
PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
|
||||||
|
}
|
||||||
|
LB {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=sext(MEM[offs]);
|
||||||
|
}
|
||||||
|
LH {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=sext(MEM[offs]{16});
|
||||||
|
}
|
||||||
|
LW {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=sext(MEM[offs]{32});
|
||||||
|
}
|
||||||
|
LBU {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=zext(MEM[offs]);
|
||||||
|
}
|
||||||
|
LHU {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=zext(MEM[offs]{16});
|
||||||
|
}
|
||||||
|
SB {
|
||||||
|
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
|
||||||
|
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1] + imm;
|
||||||
|
MEM[offs] <= X[rs2];
|
||||||
|
}
|
||||||
|
SH {
|
||||||
|
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
|
||||||
|
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1] + imm;
|
||||||
|
MEM[offs]{16} <= X[rs2];
|
||||||
|
}
|
||||||
|
SW {
|
||||||
|
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
|
||||||
|
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1] + imm;
|
||||||
|
MEM[offs]{32} <= X[rs2];
|
||||||
|
}
|
||||||
|
ADDI {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] + imm;
|
||||||
|
}
|
||||||
|
SLTI {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); //TODO: needs fix
|
||||||
|
}
|
||||||
|
SLTIU {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
val full_imm[XLEN] <= imm's;
|
||||||
|
if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
|
||||||
|
}
|
||||||
|
XORI {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] ^ imm;
|
||||||
|
}
|
||||||
|
ORI {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] | imm;
|
||||||
|
}
|
||||||
|
ANDI {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] & imm;
|
||||||
|
}
|
||||||
|
SLLI {
|
||||||
|
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
SRLI {
|
||||||
|
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
SRAI {
|
||||||
|
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
ADD {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] + X[rs2];
|
||||||
|
}
|
||||||
|
SUB {
|
||||||
|
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] - X[rs2];
|
||||||
|
}
|
||||||
|
SLL {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK);
|
||||||
|
}
|
||||||
|
SLT {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0);
|
||||||
|
}
|
||||||
|
SLTU {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0);
|
||||||
|
}
|
||||||
|
XOR {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] ^ X[rs2];
|
||||||
|
}
|
||||||
|
SRL {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK);
|
||||||
|
}
|
||||||
|
SRA {
|
||||||
|
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK);
|
||||||
|
}
|
||||||
|
OR {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] | X[rs2];
|
||||||
|
}
|
||||||
|
AND {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0) X[rd] <= X[rs1] & X[rs2];
|
||||||
|
}
|
||||||
|
FENCE {
|
||||||
|
encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111;
|
||||||
|
FENCE[fence] <= pred<<4 | succ;
|
||||||
|
}
|
||||||
|
FENCE_I(flush) {
|
||||||
|
encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ;
|
||||||
|
FENCE[fencei] <= imm;
|
||||||
|
}
|
||||||
|
ECALL(no_cont) {
|
||||||
|
encoding: b000000000000 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
raise(0, 11);
|
||||||
|
}
|
||||||
|
EBREAK(no_cont) {
|
||||||
|
encoding: b000000000001 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
raise(0, 3);
|
||||||
|
}
|
||||||
|
URET(no_cont) {
|
||||||
|
encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
leave(0);
|
||||||
|
}
|
||||||
|
SRET(no_cont) {
|
||||||
|
encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
leave(1);
|
||||||
|
}
|
||||||
|
MRET(no_cont) {
|
||||||
|
encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
leave(3);
|
||||||
|
}
|
||||||
|
WFI {
|
||||||
|
encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011;
|
||||||
|
wait(1);
|
||||||
|
}
|
||||||
|
SFENCE.VMA {
|
||||||
|
encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011;
|
||||||
|
FENCE[fencevmal] <= rs1;
|
||||||
|
FENCE[fencevmau] <= rs2;
|
||||||
|
}
|
||||||
|
CSRRW {
|
||||||
|
encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
||||||
|
val rs_val[XLEN] <= X[rs1];
|
||||||
|
if(rd!=0){
|
||||||
|
val csr_val[XLEN] <= CSR[csr];
|
||||||
|
CSR[csr] <= rs_val;
|
||||||
|
// make sure Xrd is updated once CSR write succeeds
|
||||||
|
X[rd] <= csr_val;
|
||||||
|
} else {
|
||||||
|
CSR[csr] <= rs_val;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CSRRS {
|
||||||
|
encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
||||||
|
val xrd[XLEN] <= CSR[csr];
|
||||||
|
val xrs1[XLEN] <= X[rs1];
|
||||||
|
if(rd!=0) X[rd] <= xrd;
|
||||||
|
if(rs1!=0) CSR[csr] <= xrd | xrs1;
|
||||||
|
}
|
||||||
|
CSRRC {
|
||||||
|
encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
||||||
|
val xrd[XLEN] <= CSR[csr];
|
||||||
|
val xrs1[XLEN] <= X[rs1];
|
||||||
|
if(rd!=0) X[rd] <= xrd;
|
||||||
|
if(rs1!=0) CSR[csr] <= xrd & ~xrs1;
|
||||||
|
}
|
||||||
|
CSRRWI {
|
||||||
|
encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
||||||
|
if(rd!=0) X[rd] <= CSR[csr];
|
||||||
|
CSR[csr] <= zext(zimm);
|
||||||
|
}
|
||||||
|
CSRRSI {
|
||||||
|
encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
||||||
|
val res[XLEN] <= CSR[csr];
|
||||||
|
if(zimm!=0) CSR[csr] <= res | zext(zimm);
|
||||||
|
// make sure rd is written after csr write succeeds
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
}
|
||||||
|
CSRRCI {
|
||||||
|
encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011;
|
||||||
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
||||||
|
val res[XLEN] <= CSR[csr];
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,81 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV32M extends RV32IBase {
|
||||||
|
constants {
|
||||||
|
XLEN2
|
||||||
|
}
|
||||||
|
instructions{
|
||||||
|
MUL{
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
|
||||||
|
X[rd]<= zext(res , XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
MULH {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2);
|
||||||
|
X[rd]<= zext(res >> XLEN, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
MULHSU {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
|
||||||
|
X[rd]<= zext(res >> XLEN, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
MULHU {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
|
||||||
|
X[rd]<= zext(res >> XLEN, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DIV {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
if(X[rs2]!=0)
|
||||||
|
X[rd] <= sext(X[rs1], 32) / sext(X[rs2], 32);
|
||||||
|
else
|
||||||
|
X[rd] <= -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DIVU {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
if(X[rs2]!=0)
|
||||||
|
X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32);
|
||||||
|
else
|
||||||
|
X[rd] <= -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
REM {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
if(X[rs2]!=0)
|
||||||
|
X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
|
||||||
|
else
|
||||||
|
X[rd] <= X[rs1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
REMU {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
if(X[rs2]!=0)
|
||||||
|
X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32);
|
||||||
|
else
|
||||||
|
X[rd] <= X[rs1];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,111 @@
|
||||||
|
import "RV64IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV64A extends RV64IBase{
|
||||||
|
|
||||||
|
address_spaces {
|
||||||
|
RES[8]
|
||||||
|
}
|
||||||
|
|
||||||
|
instructions{
|
||||||
|
LR.D {
|
||||||
|
encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d";
|
||||||
|
if(rd!=0){
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
X[rd]<= sext(MEM[offs]{64}, XLEN);
|
||||||
|
RES[offs]{64}<=sext(-1, 64);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SC.D {
|
||||||
|
encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[64] <= RES[offs];
|
||||||
|
if(res!=0){
|
||||||
|
MEM[offs]{64} <= X[rs2];
|
||||||
|
if(rd!=0) X[rd]<=0;
|
||||||
|
} else{
|
||||||
|
if(rd!=0) X[rd]<= 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
AMOSWAP.D{
|
||||||
|
encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
if(rd!=0) X[rd] <= sext(MEM[offs]{64});
|
||||||
|
MEM[offs]{64} <= X[rs2];
|
||||||
|
}
|
||||||
|
AMOADD.D{
|
||||||
|
encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd]<=res;
|
||||||
|
val res2[XLEN] <= res + X[rs2];
|
||||||
|
MEM[offs]{64}<=res2;
|
||||||
|
}
|
||||||
|
AMOXOR.D{
|
||||||
|
encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= res ^ X[rs2];
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
AMOAND.D{
|
||||||
|
encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= res & X[rs2];
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
AMOOR.D {
|
||||||
|
encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= res | X[rs2];
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
AMOMIN.D{
|
||||||
|
encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= choose(res s > X[rs2]s, X[rs2], res);
|
||||||
|
MEM[offs]{64} <= res;
|
||||||
|
}
|
||||||
|
AMOMAX.D{
|
||||||
|
encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= sext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= choose(res s < X[rs2]s, X[rs2], res);
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
AMOMINU.D{
|
||||||
|
encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= zext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= choose(res > X[rs2], X[rs2], res);
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
AMOMAXU.D{
|
||||||
|
encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
|
||||||
|
args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
|
||||||
|
val offs[XLEN] <= X[rs1];
|
||||||
|
val res[XLEN] <= zext(MEM[offs]{64});
|
||||||
|
if(rd!=0) X[rd] <= res;
|
||||||
|
val res2[XLEN] <= choose(res < X[rs2], X[rs2], res);
|
||||||
|
MEM[offs]{64} <= res2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,99 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV64IBase extends RV32IBase {
|
||||||
|
instructions{
|
||||||
|
LWU {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=zext(MEM[offs]{32});
|
||||||
|
}
|
||||||
|
LD{
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
|
||||||
|
args_disass:"x%rd$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1]+imm;
|
||||||
|
if(rd!=0) X[rd]<=sext(MEM[offs]{64});
|
||||||
|
}
|
||||||
|
SD{
|
||||||
|
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0] | b0100011;
|
||||||
|
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
|
||||||
|
val offs[XLEN] <= X[rs1] + sext(imm, XLEN);
|
||||||
|
MEM[offs]{64} <= X[rs2];
|
||||||
|
}
|
||||||
|
SLLI {
|
||||||
|
encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
SRLI {
|
||||||
|
encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
SRAI {
|
||||||
|
encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
|
||||||
|
}
|
||||||
|
ADDIW {
|
||||||
|
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %imm%";
|
||||||
|
if(rd != 0) X[rd] <= sext(X[rs1]{32}, XLEN) + sext(imm, XLEN);
|
||||||
|
}
|
||||||
|
SLLIW {
|
||||||
|
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shll(X[rs1]{32}, shamt);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SRLIW {
|
||||||
|
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shrl(X[rs1], shamt);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SRAIW {
|
||||||
|
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, %shamt%";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shra(X[rs1], shamt);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ADDW {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
|
||||||
|
}
|
||||||
|
SUBW {
|
||||||
|
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
|
||||||
|
}
|
||||||
|
SLLW {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shll(X[rs1], X[rs2]&0x1f);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SRLW {
|
||||||
|
encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shrl(X[rs1], X[rs2]&0x1f);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SRAW {
|
||||||
|
encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
val sh_val[32] <= shra(X[rs1], X[rs2]&0x1f);
|
||||||
|
X[rd] <= sext(sh_val, XLEN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,41 @@
|
||||||
|
import "RV64IBase.core_desc"
|
||||||
|
|
||||||
|
InsructionSet RV64M extends RV64IBase {
|
||||||
|
instructions{
|
||||||
|
MULW{
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
X[rd]<= X[rs1] * X[rs2];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DIVW {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
X[rd] <= X[rs1]s / X[rs2]s;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DIVUW {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
X[rd] <= X[rs1] / X[rs2];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
REMW {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
X[rd] <= X[rs1]s % X[rs2]s;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
REMUW {
|
||||||
|
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
|
||||||
|
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
|
||||||
|
if(rd != 0){
|
||||||
|
X[rd] <= X[rs1] % X[rs2];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,682 @@
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are met:
|
||||||
|
//
|
||||||
|
// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer in the documentation
|
||||||
|
// and/or other materials provided with the distribution.
|
||||||
|
//
|
||||||
|
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
//
|
||||||
|
// Contributors:
|
||||||
|
// eyck@minres.com - initial API and implementation
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#include <iss/iss.h>
|
||||||
|
#include <iss/debugger/gdb_session.h>
|
||||||
|
#include <easylogging++.h>
|
||||||
|
#include <memory>
|
||||||
|
#include <cstring>
|
||||||
|
|
||||||
|
#include "iss/vm_base.h"
|
||||||
|
#include "iss/arch/CORE_DEF_NAME.h"
|
||||||
|
#include "iss/arch/riscv_core.h"
|
||||||
|
#include "iss/debugger/server.h"
|
||||||
|
|
||||||
|
#include <boost/format.hpp>
|
||||||
|
|
||||||
|
namespace iss {
|
||||||
|
namespace CORE_DEF_NAME {
|
||||||
|
using namespace iss::arch;
|
||||||
|
using namespace llvm;
|
||||||
|
using namespace iss::debugger;
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
struct vm_impl;
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
struct target_adapter: public target_adapter_base {
|
||||||
|
|
||||||
|
target_adapter(server_if* srv, vm_impl<ARCH>* vm)
|
||||||
|
: target_adapter_base(srv)
|
||||||
|
, vm(vm)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/*============== Thread Control ===============================*/
|
||||||
|
|
||||||
|
/* Set generic thread */
|
||||||
|
status set_gen_thread(rp_thread_ref& thread) override;
|
||||||
|
|
||||||
|
/* Set control thread */
|
||||||
|
status set_ctrl_thread(rp_thread_ref& thread) override;
|
||||||
|
|
||||||
|
/* Get thread status */
|
||||||
|
status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
|
||||||
|
|
||||||
|
/*============= Register Access ================================*/
|
||||||
|
|
||||||
|
/* Read all registers. buf is 4-byte aligned and it is in
|
||||||
|
target byte order. If register is not available
|
||||||
|
corresponding bytes in avail_buf are 0, otherwise
|
||||||
|
avail buf is 1 */
|
||||||
|
status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
|
||||||
|
|
||||||
|
/* Write all registers. buf is 4-byte aligned and it is in target
|
||||||
|
byte order */
|
||||||
|
status write_registers(const std::vector<uint8_t>& data) override;
|
||||||
|
|
||||||
|
/* Read one register. buf is 4-byte aligned and it is in
|
||||||
|
target byte order. If register is not available
|
||||||
|
corresponding bytes in avail_buf are 0, otherwise
|
||||||
|
avail buf is 1 */
|
||||||
|
status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
|
||||||
|
|
||||||
|
/* Write one register. buf is 4-byte aligned and it is in target byte
|
||||||
|
order */
|
||||||
|
status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
|
||||||
|
|
||||||
|
/*=================== Memory Access =====================*/
|
||||||
|
|
||||||
|
/* Read memory, buf is 4-bytes aligned and it is in target
|
||||||
|
byte order */
|
||||||
|
status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
|
||||||
|
|
||||||
|
/* Write memory, buf is 4-bytes aligned and it is in target
|
||||||
|
byte order */
|
||||||
|
status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
|
||||||
|
|
||||||
|
status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
|
||||||
|
|
||||||
|
status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override;
|
||||||
|
|
||||||
|
status current_thread_query(rp_thread_ref& thread) override;
|
||||||
|
|
||||||
|
status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
|
||||||
|
|
||||||
|
status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
|
||||||
|
|
||||||
|
status raw_query(std::string in_buf, std::string& out_buf) override;
|
||||||
|
|
||||||
|
status threadinfo_query(int first, std::string& out_buf) override;
|
||||||
|
|
||||||
|
status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
|
||||||
|
|
||||||
|
status packetsize_query(std::string& out_buf) override;
|
||||||
|
|
||||||
|
status add_break(int type, uint64_t addr, unsigned int length) override;
|
||||||
|
|
||||||
|
status remove_break(int type, uint64_t addr, unsigned int length) override;
|
||||||
|
|
||||||
|
status resume_from_addr(bool step, int sig, uint64_t addr) override;
|
||||||
|
|
||||||
|
protected:
|
||||||
|
static inline constexpr addr_t map_addr(const addr_t& i){
|
||||||
|
return i;
|
||||||
|
}
|
||||||
|
|
||||||
|
vm_impl<ARCH>* vm;
|
||||||
|
rp_thread_ref thread_idx;
|
||||||
|
};
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
struct vm_impl: public vm::vm_base<ARCH> {
|
||||||
|
using super = typename vm::vm_base<ARCH>;
|
||||||
|
using virt_addr_t = typename super::virt_addr_t;
|
||||||
|
using phys_addr_t = typename super::phys_addr_t;
|
||||||
|
using code_word_t = typename super::code_word_t;
|
||||||
|
using addr_t = typename super::addr_t ;
|
||||||
|
|
||||||
|
vm_impl();
|
||||||
|
|
||||||
|
vm_impl(ARCH& core, bool dump=false);
|
||||||
|
|
||||||
|
void enableDebug(bool enable) {
|
||||||
|
super::sync_exec=super::ALL_SYNC;
|
||||||
|
}
|
||||||
|
|
||||||
|
target_adapter_if* accquire_target_adapter(server_if* srv){
|
||||||
|
debugger_if::dbg_enabled=true;
|
||||||
|
if(vm::vm_base<ARCH>::tgt_adapter==nullptr)
|
||||||
|
vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this);
|
||||||
|
return vm::vm_base<ARCH>::tgt_adapter;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
protected:
|
||||||
|
|
||||||
|
template<typename T> inline
|
||||||
|
llvm::ConstantInt* size(T type){
|
||||||
|
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
|
||||||
|
}
|
||||||
|
|
||||||
|
inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const {
|
||||||
|
return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
|
||||||
|
}
|
||||||
|
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override;
|
||||||
|
|
||||||
|
void gen_leave_behavior(llvm::BasicBlock* leave_blk) override;
|
||||||
|
|
||||||
|
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
|
||||||
|
|
||||||
|
void gen_leave_trap(unsigned lvl);
|
||||||
|
|
||||||
|
void gen_wait(unsigned type);
|
||||||
|
|
||||||
|
void gen_trap_behavior(llvm::BasicBlock*) override;
|
||||||
|
|
||||||
|
void gen_trap_check(llvm::BasicBlock* bb);
|
||||||
|
|
||||||
|
inline
|
||||||
|
void gen_set_pc(virt_addr_t pc, unsigned reg_num){
|
||||||
|
llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN));
|
||||||
|
this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
|
||||||
|
}
|
||||||
|
|
||||||
|
inline
|
||||||
|
llvm::Value* get_reg_ptr(unsigned i){
|
||||||
|
void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i);
|
||||||
|
llvm::PointerType* ptrType=nullptr;
|
||||||
|
switch (traits<ARCH>::reg_bit_width(i)>>3) {
|
||||||
|
case 8:
|
||||||
|
ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext());
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext());
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext());
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext());
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
throw std::runtime_error("unsupported access with");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return llvm::ConstantExpr::getIntToPtr(
|
||||||
|
llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt(
|
||||||
|
8/*bits*/ * sizeof(uint8_t*),
|
||||||
|
reinterpret_cast<uint64_t>(ptr)
|
||||||
|
)),
|
||||||
|
ptrType);
|
||||||
|
}
|
||||||
|
|
||||||
|
inline
|
||||||
|
void gen_set_pc(virt_addr_t pc){
|
||||||
|
llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
|
||||||
|
super::gen_set_reg(traits<ARCH>::PC, pc_l);
|
||||||
|
}
|
||||||
|
|
||||||
|
// some compile time constants
|
||||||
|
enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111};
|
||||||
|
enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2};
|
||||||
|
enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)};
|
||||||
|
|
||||||
|
using this_class = vm_impl<ARCH>;
|
||||||
|
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb);
|
||||||
|
compile_func lut[LUT_SIZE];
|
||||||
|
|
||||||
|
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
|
||||||
|
std::array<compile_func, LUT_SIZE> lut_11;
|
||||||
|
|
||||||
|
compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11};
|
||||||
|
|
||||||
|
const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
|
||||||
|
|
||||||
|
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){
|
||||||
|
if(pos<0){
|
||||||
|
lut[idx]=f;
|
||||||
|
} else {
|
||||||
|
auto bitmask = 1UL<<pos;
|
||||||
|
if((mask & bitmask)==0){
|
||||||
|
expand_bit_mask(pos-1, mask, value, valid, idx, lut, f);
|
||||||
|
} else {
|
||||||
|
if((valid & bitmask) == 0) {
|
||||||
|
expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f);
|
||||||
|
expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f);
|
||||||
|
} else {
|
||||||
|
auto new_val = idx<<1;
|
||||||
|
if((value&bitmask)!=0)
|
||||||
|
new_val++;
|
||||||
|
expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
inline uint32_t extract_fields(uint32_t val){
|
||||||
|
return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){
|
||||||
|
if(pos>=0) {
|
||||||
|
auto bitmask = 1UL<<pos;
|
||||||
|
if((mask & bitmask)==0){
|
||||||
|
lut_val = extract_fields(pos-1, val, mask, lut_val);
|
||||||
|
} else {
|
||||||
|
auto new_val = lut_val<<1;
|
||||||
|
if((val&bitmask)!=0)
|
||||||
|
new_val++;
|
||||||
|
lut_val = extract_fields(pos-1, val, mask, new_val);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return lut_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
private:
|
||||||
|
/****************************************************************************
|
||||||
|
* start opcode definitions
|
||||||
|
****************************************************************************/
|
||||||
|
struct InstructionDesriptor {
|
||||||
|
size_t length;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t mask;
|
||||||
|
compile_func op;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* «start generated code» */
|
||||||
|
InstructionDesriptor instr_descr[0] = {};
|
||||||
|
/* «end generated code» */
|
||||||
|
/****************************************************************************
|
||||||
|
* end opcode definitions
|
||||||
|
****************************************************************************/
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
|
||||||
|
//this->gen_sync(iss::PRE_SYNC);
|
||||||
|
this->builder->CreateStore(
|
||||||
|
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
|
||||||
|
get_reg_ptr(traits<ARCH>::PC), true);
|
||||||
|
this->builder->CreateStore(
|
||||||
|
this->builder->CreateAdd(
|
||||||
|
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
|
||||||
|
this->gen_const(64U, 1)),
|
||||||
|
get_reg_ptr(traits<ARCH>::ICOUNT), true);
|
||||||
|
if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
|
||||||
|
pc=pc+((instr&3) == 3?4:2);
|
||||||
|
this->gen_raise_trap(0, 2); // illegal instruction trap
|
||||||
|
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
|
||||||
|
this->gen_trap_check(this->leave_blk);
|
||||||
|
return std::make_tuple(iss::vm::BRANCH, nullptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
template<typename CODE_WORD>
|
||||||
|
void debug_fn(CODE_WORD insn){
|
||||||
|
volatile CODE_WORD x=insn;
|
||||||
|
insn=2*x;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
vm_impl<ARCH>::vm_impl(){
|
||||||
|
this(new ARCH());
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
|
||||||
|
qlut[0] = lut_00.data();
|
||||||
|
qlut[1] = lut_01.data();
|
||||||
|
qlut[2] = lut_10.data();
|
||||||
|
qlut[3] = lut_11.data();
|
||||||
|
for(auto instr: instr_descr){
|
||||||
|
auto quantrant = instr.value&0x3;
|
||||||
|
expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op);
|
||||||
|
}
|
||||||
|
this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync());
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){
|
||||||
|
// we fetch at max 4 byte, alignment is 2
|
||||||
|
code_word_t insn = 0;
|
||||||
|
iss::addr_t paddr;
|
||||||
|
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
|
||||||
|
try {
|
||||||
|
uint8_t* const data = (uint8_t*)&insn;
|
||||||
|
paddr=this->core.v2p(pc);
|
||||||
|
if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
|
||||||
|
auto res = this->core.read_mem(paddr, 2, data);
|
||||||
|
if(res!=iss::Ok)
|
||||||
|
throw trap_access(1, pc.val);
|
||||||
|
if((insn & 0x3) == 0x3){ // this is a 32bit instruction
|
||||||
|
res = this->core.read_mem(this->core.v2p(pc+2), 2, data+2);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
auto res = this->core.read_mem(paddr, 4, data);
|
||||||
|
if(res!=iss::Ok)
|
||||||
|
throw trap_access(1, pc.val);
|
||||||
|
}
|
||||||
|
} catch(trap_access& ta){
|
||||||
|
throw trap_access(ta.id, pc.val);
|
||||||
|
}
|
||||||
|
if(insn==0x0000006f)
|
||||||
|
throw vm::simulation_stopped(0);
|
||||||
|
// curr pc on stack
|
||||||
|
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
|
||||||
|
++inst_cnt;
|
||||||
|
auto lut_val = extract_fields(insn);
|
||||||
|
auto f = qlut[insn&0x3][lut_val];
|
||||||
|
if (f==nullptr){
|
||||||
|
f=&this_class::illegal_intruction;
|
||||||
|
}
|
||||||
|
return (this->*f)(pc, insn, this_block);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
|
||||||
|
this->builder->SetInsertPoint(leave_blk);
|
||||||
|
this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
|
||||||
|
auto* TRAP_val = this->gen_const(traits<ARCH>::XLEN, 0x80<<24| (cause<<16) | trap_id );
|
||||||
|
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){
|
||||||
|
std::vector<llvm::Value*> args {
|
||||||
|
this->core_ptr,
|
||||||
|
llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
|
||||||
|
};
|
||||||
|
this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
|
||||||
|
auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8);
|
||||||
|
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
void vm_impl<ARCH>::gen_wait(unsigned type){
|
||||||
|
std::vector<llvm::Value*> args {
|
||||||
|
this->core_ptr,
|
||||||
|
llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
|
||||||
|
};
|
||||||
|
this->builder->CreateCall(this->mod->getFunction("wait"), args);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock* trap_blk){
|
||||||
|
this->builder->SetInsertPoint(trap_blk);
|
||||||
|
auto* trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
|
||||||
|
std::vector<llvm::Value*> args {
|
||||||
|
this->core_ptr,
|
||||||
|
this->adj_to64(trap_state_val),
|
||||||
|
this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))
|
||||||
|
};
|
||||||
|
this->builder->CreateCall(this->mod->getFunction("enter_trap"), args);
|
||||||
|
auto* trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
|
||||||
|
this->builder->CreateRet(trap_addr_val);
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH> inline
|
||||||
|
void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
|
||||||
|
auto* v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
|
||||||
|
this->gen_cond_branch(
|
||||||
|
this->builder->CreateICmp(
|
||||||
|
ICmpInst::ICMP_EQ,
|
||||||
|
v,
|
||||||
|
llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
|
||||||
|
bb,
|
||||||
|
this->trap_blk, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace CORE_DEF_NAME
|
||||||
|
|
||||||
|
#define CREATE_FUNCS(ARCH) \
|
||||||
|
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
|
||||||
|
std::unique_ptr<CORE_DEF_NAME::vm_impl<ARCH> > ret = std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump);\
|
||||||
|
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
|
||||||
|
return ret;\
|
||||||
|
}\
|
||||||
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
|
||||||
|
return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
|
||||||
|
}\
|
||||||
|
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
|
||||||
|
return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
|
||||||
|
}\
|
||||||
|
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
|
||||||
|
return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
|
||||||
|
}
|
||||||
|
|
||||||
|
CREATE_FUNCS(arch::CORE_DEF_NAME)
|
||||||
|
|
||||||
|
namespace CORE_DEF_NAME {
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
|
||||||
|
thread_idx=thread;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
|
||||||
|
thread_idx=thread;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
|
||||||
|
alive=1;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* List threads. If first is non-zero then start from the first thread,
|
||||||
|
* otherwise start from arg, result points to array of threads to be
|
||||||
|
* filled out, result size is number of elements in the result,
|
||||||
|
* num points to the actual number of threads found, done is
|
||||||
|
* set if all threads are processed.
|
||||||
|
*/
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num,
|
||||||
|
size_t& num, bool& done) {
|
||||||
|
if(first==0){
|
||||||
|
result.clear();
|
||||||
|
result.push_back(thread_idx);
|
||||||
|
num=1;
|
||||||
|
done=true;
|
||||||
|
return Ok;
|
||||||
|
} else
|
||||||
|
return NotSupported;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
|
||||||
|
thread=thread_idx;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
||||||
|
LOG(TRACE)<<"reading target registers";
|
||||||
|
//return idx<0?:;
|
||||||
|
data.clear();
|
||||||
|
avail.clear();
|
||||||
|
std::vector<uint8_t> reg_data;
|
||||||
|
for(size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no){
|
||||||
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
||||||
|
auto reg_width=reg_bit_width/8;
|
||||||
|
reg_data.resize(reg_width);
|
||||||
|
vm->get_arch()->get_reg(reg_no, reg_data);
|
||||||
|
for(size_t j=0; j<reg_data.size(); ++j){
|
||||||
|
data.push_back(reg_data[j]);
|
||||||
|
avail.push_back(0xff);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
// work around fill with F type registers
|
||||||
|
if(arch::traits<ARCH>::NUM_REGS < 65){
|
||||||
|
auto reg_width=sizeof(typename arch::traits<ARCH>::reg_t);
|
||||||
|
for(size_t reg_no = 0; reg_no < 33; ++reg_no){
|
||||||
|
for(size_t j=0; j<reg_width; ++j){
|
||||||
|
data.push_back(0x0);
|
||||||
|
avail.push_back(0x00);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
|
||||||
|
size_t data_index=0;
|
||||||
|
auto reg_count=arch::traits<ARCH>::NUM_REGS;
|
||||||
|
std::vector<uint8_t> reg_data;
|
||||||
|
for(size_t reg_no = 0; reg_no < reg_count; ++reg_no){
|
||||||
|
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
|
||||||
|
auto reg_width=reg_bit_width/8;
|
||||||
|
vm->get_arch()->set_reg(reg_no, std::vector<uint8_t>(data.begin()+data_index, data.begin()+data_index+reg_width));
|
||||||
|
data_index+=reg_width;
|
||||||
|
}
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
|
||||||
|
if(reg_no<65){
|
||||||
|
//auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no))/8;
|
||||||
|
data.resize(0);
|
||||||
|
vm->get_arch()->get_reg(reg_no, data);
|
||||||
|
avail.resize(data.size());
|
||||||
|
std::fill(avail.begin(), avail.end(), 0xff);
|
||||||
|
} else {
|
||||||
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no-65);
|
||||||
|
data.resize(sizeof(typename traits<ARCH>::reg_t));
|
||||||
|
avail.resize(sizeof(typename traits<ARCH>::reg_t));
|
||||||
|
std::fill(avail.begin(), avail.end(), 0xff);
|
||||||
|
vm->get_arch()->read_mem(a, data.size(), data.data());
|
||||||
|
}
|
||||||
|
return data.size()>0?Ok:Err;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
|
||||||
|
if(reg_no<65)
|
||||||
|
vm->get_arch()->set_reg(reg_no, data);
|
||||||
|
else {
|
||||||
|
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65);
|
||||||
|
vm->get_arch()->write_mem(a, data.size(), data.data());
|
||||||
|
}
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
|
||||||
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
||||||
|
auto f = [&]()->status {
|
||||||
|
return vm->get_arch()->read_mem(a, data.size(), data.data());
|
||||||
|
};
|
||||||
|
return srv->execute_syncronized(f);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
|
||||||
|
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
|
||||||
|
return srv->execute_syncronized(&arch_if::write_mem, vm->get_arch(), a, data.size(), data.data());
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
|
||||||
|
return NotSupported;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
|
||||||
|
text=0;
|
||||||
|
data=0;
|
||||||
|
bss=0;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) {
|
||||||
|
return NotSupported;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) {
|
||||||
|
return NotSupported;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
|
||||||
|
if(first){
|
||||||
|
std::stringstream ss;
|
||||||
|
ss<<"m"<<std::hex<<thread_idx.val;
|
||||||
|
out_buf=ss.str();
|
||||||
|
} else {
|
||||||
|
out_buf="l";
|
||||||
|
}
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
|
||||||
|
char buf[20];
|
||||||
|
memset(buf, 0, 20);
|
||||||
|
sprintf (buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
|
||||||
|
out_buf=buf;
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
|
||||||
|
out_buf="PacketSize=1000";
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
|
||||||
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
||||||
|
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length});
|
||||||
|
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val);
|
||||||
|
LOG(TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
||||||
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
|
||||||
|
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
|
||||||
|
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
|
||||||
|
// TODO: check length of addr range
|
||||||
|
if(handle){
|
||||||
|
LOG(TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
|
||||||
|
target_adapter_base::bp_lut.removeEntry(handle);
|
||||||
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||||||
|
return Ok;
|
||||||
|
}
|
||||||
|
LOG(TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
|
||||||
|
return Err;
|
||||||
|
}
|
||||||
|
|
||||||
|
template<typename ARCH>
|
||||||
|
status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
|
||||||
|
unsigned reg_no = arch::traits<ARCH>::PC;
|
||||||
|
std::vector<uint8_t> data(8);
|
||||||
|
*(reinterpret_cast<uint64_t*>(&data[0]))=addr;
|
||||||
|
vm->get_arch()->set_reg(reg_no, data);
|
||||||
|
return resume_from_current(step, sig);
|
||||||
|
}
|
||||||
|
} // namespace CORE_DEF_NAME
|
||||||
|
} // namespace iss
|
|
@ -0,0 +1,147 @@
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are met:
|
||||||
|
//
|
||||||
|
// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer in the documentation
|
||||||
|
// and/or other materials provided with the distribution.
|
||||||
|
//
|
||||||
|
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
//
|
||||||
|
// Contributors:
|
||||||
|
// eyck@minres.com - initial API and implementation
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
#include "util/ities.h"
|
||||||
|
#include <easylogging++.h>
|
||||||
|
|
||||||
|
#include <elfio/elfio.hpp>
|
||||||
|
#include <iss/arch/minrv_ima.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
#include <ihex.h>
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#include <fstream>
|
||||||
|
#include <cstdio>
|
||||||
|
#include <cstring>
|
||||||
|
|
||||||
|
using namespace iss::arch;
|
||||||
|
|
||||||
|
minrv_ima::minrv_ima() {
|
||||||
|
reg.icount=0;
|
||||||
|
}
|
||||||
|
|
||||||
|
minrv_ima::~minrv_ima(){
|
||||||
|
}
|
||||||
|
|
||||||
|
void minrv_ima::reset(uint64_t address) {
|
||||||
|
for(size_t i=0; i<traits<minrv_ima>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<minrv_ima>::reg_t),0));
|
||||||
|
reg.PC=address;
|
||||||
|
reg.NEXT_PC=reg.PC;
|
||||||
|
reg.trap_state=0;
|
||||||
|
reg.machine_state=0x3;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t* minrv_ima::get_regs_base_ptr(){
|
||||||
|
return reinterpret_cast<uint8_t*>(®);
|
||||||
|
}
|
||||||
|
|
||||||
|
void minrv_ima::get_reg(short idx, std::vector<uint8_t>& value) {
|
||||||
|
if(idx<traits<minrv_ima>::NUM_REGS){
|
||||||
|
value.resize(traits<minrv_ima>::reg_byte_offset(idx+1)-traits<minrv_ima>::reg_byte_offset(idx));
|
||||||
|
uint8_t* r_ptr= ((uint8_t*)®)+traits<minrv_ima>::reg_byte_offset(idx);
|
||||||
|
std::copy(r_ptr, r_ptr+sizeof(traits<minrv_ima>::reg_t), value.begin());
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void minrv_ima::set_reg(short idx, const std::vector<uint8_t>& value) {
|
||||||
|
if(idx < traits<minrv_ima>::NUM_REGS){
|
||||||
|
uint8_t* r_ptr= ((uint8_t*)®)+traits<minrv_ima>::reg_byte_offset(idx);
|
||||||
|
std::copy(value.begin(), value.end(), r_ptr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bool minrv_ima::get_flag(int flag){
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
void minrv_ima::set_flag(int flag, bool value){
|
||||||
|
}
|
||||||
|
|
||||||
|
void minrv_ima::update_flags(operations op, uint64_t r0, uint64_t r1){
|
||||||
|
}
|
||||||
|
|
||||||
|
minrv_ima::phys_addr_t minrv_ima::v2p(const iss::addr_t& pc) {
|
||||||
|
return phys_addr_t(pc); //change logical address to physical address
|
||||||
|
}
|
||||||
|
|
||||||
|
using namespace ELFIO;
|
||||||
|
|
||||||
|
/*
|
||||||
|
void minrv_ima::loadFile(std::string name, int type) {
|
||||||
|
FILE* fp = fopen(name.c_str(), "r");
|
||||||
|
if(fp){
|
||||||
|
char buf[5];
|
||||||
|
auto n = fread(buf, 1,4,fp);
|
||||||
|
if(n!=4) throw std::runtime_error("input file has insufficient size");
|
||||||
|
buf[4]=0;
|
||||||
|
if(strcmp(buf+1, "ELF")==0){
|
||||||
|
fclose(fp);
|
||||||
|
//Create elfio reader
|
||||||
|
elfio reader;
|
||||||
|
// Load ELF data
|
||||||
|
if ( !reader.load( name ) ) throw std::runtime_error("could not process elf file");
|
||||||
|
// check elf properties
|
||||||
|
//TODO: fix ELFCLASS like:
|
||||||
|
// if ( reader.get_class() != ELFCLASS32 ) throw std::runtime_error("wrong elf class in file");
|
||||||
|
if ( reader.get_type() != ET_EXEC ) throw std::runtime_error("wrong elf type in file");
|
||||||
|
//TODO: fix machine type like:
|
||||||
|
// if ( reader.get_machine() != EM_RISCV ) throw std::runtime_error("wrong elf machine in file");
|
||||||
|
auto sec_num = reader.sections.size();
|
||||||
|
auto seg_num = reader.segments.size();
|
||||||
|
for ( int i = 0; i < seg_num; ++i ) {
|
||||||
|
const auto pseg = reader.segments[i];
|
||||||
|
const auto fsize=pseg->get_file_size(); // 0x42c/0x0
|
||||||
|
const auto seg_data=pseg->get_data();
|
||||||
|
if(fsize>0){
|
||||||
|
this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, traits<minrv_ima>::MEM, pseg->get_virtual_address()), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
fseek(fp, 0, SEEK_SET);
|
||||||
|
if(type<0) throw std::runtime_error("a memory type needs to be specified for IHEX files");
|
||||||
|
IHexRecord irec;
|
||||||
|
while (Read_IHexRecord(&irec, fp) == IHEX_OK) {
|
||||||
|
this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, type, irec.address), irec.dataLen, irec.data);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
LOG(ERROR)<<"Could not open input file "<<name;
|
||||||
|
throw std::runtime_error("Could not open input file");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
|
@ -0,0 +1,103 @@
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without
|
||||||
|
// modification, are permitted provided that the following conditions are met:
|
||||||
|
//
|
||||||
|
// 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer.
|
||||||
|
//
|
||||||
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
// this list of conditions and the following disclaimer in the documentation
|
||||||
|
// and/or other materials provided with the distribution.
|
||||||
|
//
|
||||||
|
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
// may be used to endorse or promote products derived from this software
|
||||||
|
// without specific prior written permission.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
// POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
//
|
||||||
|
// Contributors:
|
||||||
|
// eyck@minres.com - initial API and implementation
|
||||||
|
////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
#include <cli_options.h>
|
||||||
|
#include <iss/iss.h>
|
||||||
|
#include <iostream>
|
||||||
|
|
||||||
|
#include <iss/arch/minrv_ima.h>
|
||||||
|
#ifndef WITHOUT_LLVM
|
||||||
|
#include <iss/jit/MCJIThelper.h>
|
||||||
|
#endif
|
||||||
|
#ifdef WITH_SYSTEMC
|
||||||
|
#include <sysc/kernel/sc_externs.h>
|
||||||
|
#endif
|
||||||
|
#include <boost/lexical_cast.hpp>
|
||||||
|
|
||||||
|
namespace po= boost::program_options;
|
||||||
|
|
||||||
|
INITIALIZE_EASYLOGGINGPP
|
||||||
|
|
||||||
|
int main(int argc, char *argv[]) {
|
||||||
|
try{
|
||||||
|
/** Define and parse the program options
|
||||||
|
*/
|
||||||
|
po::variables_map vm;
|
||||||
|
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
|
||||||
|
configure_default_logger(vm);
|
||||||
|
// configure the connection logger
|
||||||
|
configure_debugger_logger();
|
||||||
|
|
||||||
|
// application code comes here //
|
||||||
|
iss::init_jit(argc, argv);
|
||||||
|
if(vm.count("systemc")){
|
||||||
|
//#ifdef WITH_SYSTEMC
|
||||||
|
// return sc_core::sc_elab_and_sim(argc, argv);
|
||||||
|
//#else
|
||||||
|
std::cerr<<"SystemC simulation is currently not supported, please rebuild with -DWITH_SYSTEMC"<<std::endl;
|
||||||
|
//#endif
|
||||||
|
} else {
|
||||||
|
bool dump=vm.count("dump-ir");
|
||||||
|
// instantiate the simulator
|
||||||
|
std::unique_ptr<iss::vm_if> cpu = vm.count("gdb-port")?
|
||||||
|
iss::create<iss::arch::minrv_ima>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
|
||||||
|
iss::create<iss::arch::minrv_ima>("rv32ima", dump);
|
||||||
|
if(vm.count("elf")){
|
||||||
|
for(std::string input: vm["elf"].as<std::vector<std::string> >())
|
||||||
|
cpu->get_arch()->load_file(input);
|
||||||
|
} else if(vm.count("mem")){
|
||||||
|
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::minrv_ima>::MEM);
|
||||||
|
} //else
|
||||||
|
// LOG(FATAL)<<"At least one (flash-)input file (ELF or IHEX) needs to be specified";
|
||||||
|
|
||||||
|
configure_disass_logger(vm);
|
||||||
|
if(vm.count("disass")){
|
||||||
|
cpu->setDisassEnabled(true);
|
||||||
|
}
|
||||||
|
if(vm.count("reset")){
|
||||||
|
auto str = vm["reset"].as<std::string>();
|
||||||
|
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
|
||||||
|
cpu->reset(start_address);
|
||||||
|
} else {
|
||||||
|
cpu->reset();
|
||||||
|
}
|
||||||
|
return cpu->start(vm["cycles"].as<int64_t>());
|
||||||
|
}
|
||||||
|
} catch(std::exception& e){
|
||||||
|
LOG(ERROR) << "Unhandled Exception reached the top of main: "
|
||||||
|
<< e.what() << ", application will now exit" << std::endl;
|
||||||
|
return ERROR_UNHANDLED_EXCEPTION;
|
||||||
|
}
|
||||||
|
}
|
|
@ -0,0 +1,38 @@
|
||||||
|
import "RV32IBase.core_desc"
|
||||||
|
import "RV32M.core_desc"
|
||||||
|
import "RV32A.core_desc"
|
||||||
|
import "RV32C.core_desc"
|
||||||
|
//import "RV64IBase.core_desc"
|
||||||
|
//import "RV64M.core_desc"
|
||||||
|
//import "RV64A.core_desc"
|
||||||
|
|
||||||
|
Core MinRV_IMA provides RV32IBase,RV32M,RV32A, RV32CI {
|
||||||
|
template:"vm_riscv.in.cpp";
|
||||||
|
constants {
|
||||||
|
XLEN:=32;
|
||||||
|
XLEN2:=64;
|
||||||
|
XLEN_BIT_MASK:=0x1f;
|
||||||
|
PCLEN:=32;
|
||||||
|
fence:=0;
|
||||||
|
fencei:=1;
|
||||||
|
fencevmal:=2;
|
||||||
|
fencevmau:=3;
|
||||||
|
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
|
||||||
|
MISA_VAL:=0b01000000000101000001000100000001;
|
||||||
|
PGSIZE := 4096; //1 << 12;
|
||||||
|
PGMASK := 4095; //PGSIZE-1
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
Core RV64IMA provides RV64IBase, RV64M, RV64A {
|
||||||
|
template:"vm_riscv.in.cpp";
|
||||||
|
constants {
|
||||||
|
XLEN:=64;
|
||||||
|
XLEN_BIT_MASK:=0x3f;
|
||||||
|
PCLEN:=64;
|
||||||
|
fence:=0;
|
||||||
|
fencei:=1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
*/
|
|
@ -0,0 +1 @@
|
||||||
|
Subproject commit 872788c447696f228a817f7cd38746d412ebb537
|
Loading…
Reference in New Issue