Added RV32F extension, fixed RV32M bugs

riscv/gen_input/templates/incl-CORENAME.h.gtl

@@ -100,6 +100,8 @@ struct traits<${coreDef.name.toLowerCase()}> {
 
     enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
 
+	constexpr static bool has_fp_regs = ${allRegs.find {it.name=='FCSR'}!= null ?'true':'false'};
+    
 };
 
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -112,8 +114,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
     ${coreDef.name.toLowerCase()}();
     ~${coreDef.name.toLowerCase()}();
 
-	const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
-	
     void reset(uint64_t address=0) override;
 
     uint8_t* get_regs_base_ptr() override;
@@ -158,9 +158,16 @@ protected:
     } reg;
 
     std::array<address_type, 4> addr_mode;
-
-    uint64_t cycles = 0;
-
+    
+<%
+def fcsr = allRegs.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
+<%} else { %>
+	uint32_t get_fcsr(){return 0;}
+	void set_fcsr(uint32_t val){}
+<%}%>
 };
 
 }

riscv/gen_input/templates/src-CORENAME.cpp.gtl

@@ -68,6 +68,7 @@ uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
     return reinterpret_cast<uint8_t*>(&reg);
 }
 
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::v2p(const iss::addr_t& pc) {
-    return phys_addr_t(pc); //change logical address to physical address
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
+    return phys_addr_t(pc); // change logical address to physical address
 }
+

riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl

@@ -48,6 +48,12 @@
 #include <array>
 
 namespace iss {
+namespace vm {
+namespace fp_impl{
+void add_fp_functions_2_module(llvm::Module *mod);
+}
+}
+
 namespace ${coreDef.name.toLowerCase()} {
 using namespace iss::arch;
 using namespace llvm;
@@ -81,6 +87,11 @@ protected:
         return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
     }
 
+    void setup_module(llvm::Module* m) override {
+        super::setup_module(m);
+        vm::fp_impl::add_fp_functions_2_module(m);
+    }
+
     inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
                                    unsigned size) const {
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
@@ -106,6 +117,10 @@ protected:
         return this->builder.CreateLoad(get_reg_ptr(i), false);
     }
 
+    llvm::Value* gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args);
+
+    llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*);
+
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
         llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
                                                                   this->get_type(traits<ARCH>::XLEN));
@@ -310,7 +325,16 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
                           bb, this->trap_blk, 1);
 }
 
-} // namespace ${coreDef.name.toLowerCase()}
+template<typename ARCH>
+inline llvm::Value* vm_impl<ARCH>::gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args) {
+        return this->builder.CreateCall(this->mod->getFunction(fname), args);
+}
+
+template<typename ARCH>
+inline llvm::Value* vm_impl<ARCH>::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) {
+}
+
+} // namespace rv32imacf
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {