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Added RV32F extension, fixed RV32M bugs

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This commit is contained in:
Eyck Jentzsch
2018-04-24 11:05:11 +02:00
parent bc7450dad2
commit 48ad30dcae
21 changed files with 8208 additions and 512 deletions
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77
riscv/gen_input/RV32C.core_desc
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@ -1,6 +1,6 @@
import "RV32IBase.core_desc"
InsructionSet RV32CI {
InsructionSet RV32IC {
constants {
XLEN
}
@ -197,7 +197,64 @@ InsructionSet RV32CI {
}
}
InsructionSet RV32CF extends RV32CI {
InsructionSet RV32FC extends RV32IC{
constants {
XLEN, FLEN
}
address_spaces {
MEM[8]
}
registers {
[31:0] X[XLEN],
[31:0] F[FLEN]
}
instructions{
C.FLW {
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
val rs1_idx[5] <= rs1+8;
val rd_idx[5] <= rd+8;
val offs[XLEN] <= X[rs1_idx]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd_idx] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd_idx] <= upper*2 | res;
}
}
C.FSW {
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
val rs1_idx[5] <= rs1+8;
val rs2_idx[5] <= rs2+8;
val offs[XLEN] <= X[rs1_idx]+uimm;
MEM[offs]{32}<=F[rs2_idx]{32};
}
C.FLWSP {
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
args_disass:"f%rd$d, %uimm%(x2)";
val x2_idx[5] <= 2;
val offs[XLEN] <= X[x2_idx]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
}
C.FSWSP {
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
args_disass:"f%rs2$d, %uimm%(x2), ";
val x2_idx[5] <= 2;
val offs[XLEN] <= X[x2_idx]+uimm;
MEM[offs]{32}<=F[rs2];
}
}
}
InsructionSet RV32DC extends RV32IC{
constants {
XLEN, FLEN
}
@ -212,31 +269,19 @@ InsructionSet RV32CF extends RV32CI {
C.FLD { //(RV32/64)
encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
}
C.FLW {//(RV32)
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
}
C.FSD { //(RV32/64)
encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
}
C.FSW {//(RV32)
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
}
C.FLDSP {//(RV32/64)
encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
}
C.FLWSP {//RV32
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
}
C.FSDSP {//(RV32/64)
encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
}
C.FSWSP {//(RV32)
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
}
}
}
InsructionSet RV64CI extends RV32CI {
InsructionSet RV64IC extends RV32IC {
constants {
XLEN
}
@ -284,7 +329,7 @@ InsructionSet RV64CI extends RV32CI {
}
}
InsructionSet RV128CI extends RV64CI {
InsructionSet RV128IC extends RV64IC {
constants {
XLEN
}