VP/HIFIVE1-VP
8
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Added RV32F extension, fixed RV32M bugs

Browse Source
This commit is contained in:
Eyck Jentzsch
2018-04-24 11:05:11 +02:00
parent bc7450dad2
commit 48ad30dcae
21 changed files with 8208 additions and 512 deletions
Download Patch File Download Diff File Expand all files Collapse all files

77
riscv/gen_input/RV32C.core_desc
View File

@ -1,6 +1,6 @@
import "RV32IBase.core_desc"
InsructionSet RV32CI {
InsructionSet RV32IC {
constants {
XLEN
}
@ -197,7 +197,64 @@ InsructionSet RV32CI {
}
}
InsructionSet RV32CF extends RV32CI {
InsructionSet RV32FC extends RV32IC{
constants {
XLEN, FLEN
}
address_spaces {
MEM[8]
}
registers {
[31:0] X[XLEN],
[31:0] F[FLEN]
}
instructions{
C.FLW {
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
val rs1_idx[5] <= rs1+8;
val rd_idx[5] <= rd+8;
val offs[XLEN] <= X[rs1_idx]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd_idx] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd_idx] <= upper*2 | res;
}
}
C.FSW {
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
val rs1_idx[5] <= rs1+8;
val rs2_idx[5] <= rs2+8;
val offs[XLEN] <= X[rs1_idx]+uimm;
MEM[offs]{32}<=F[rs2_idx]{32};
}
C.FLWSP {
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
args_disass:"f%rd$d, %uimm%(x2)";
val x2_idx[5] <= 2;
val offs[XLEN] <= X[x2_idx]+uimm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
}
C.FSWSP {
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
args_disass:"f%rs2$d, %uimm%(x2), ";
val x2_idx[5] <= 2;
val offs[XLEN] <= X[x2_idx]+uimm;
MEM[offs]{32}<=F[rs2];
}
}
}
InsructionSet RV32DC extends RV32IC{
constants {
XLEN, FLEN
}
@ -212,31 +269,19 @@ InsructionSet RV32CF extends RV32CI {
C.FLD { //(RV32/64)
encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
}
C.FLW {//(RV32)
encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
}
C.FSD { //(RV32/64)
encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
}
C.FSW {//(RV32)
encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
}
C.FLDSP {//(RV32/64)
encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
}
C.FLWSP {//RV32
encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
}
C.FSDSP {//(RV32/64)
encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
}
C.FSWSP {//(RV32)
encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
}
}
}
InsructionSet RV64CI extends RV32CI {
InsructionSet RV64IC extends RV32IC {
constants {
XLEN
}
@ -284,7 +329,7 @@ InsructionSet RV64CI extends RV32CI {
}
}
InsructionSet RV128CI extends RV64CI {
InsructionSet RV128IC extends RV64IC {
constants {
XLEN
}

231
riscv/gen_input/RV32F.core_desc
View File

@ -2,104 +2,293 @@ import "RV32IBase.core_desc"
InsructionSet RV32F extends RV32IBase{
constants {
FLEN, fcsr
FLEN, FFLAG_MASK
}
registers {
[31:0] F[FLEN]
[31:0] F[FLEN], FCSR[32]
}
instructions{
FLW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
args_disass:"f%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
F[rd]<=MEM[offs];
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
}
FSW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
args_disass:"f%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
MEM[offs]<=F[rs2];
MEM[offs]{32}<=F[rs2]{32};
}
FMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
F[rd]f<= F[rs1]f * F[rs2]f * F[rs3]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
F[rd]f<=F[rs1]f * F[rs2]f -F[rs3]f;
}
FNMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
F[rd]f<=-F[rs1]f * F[rs2]f- F[rs3]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
F[rd]f<=-F[rs1]f*F[rs2]f+F[rs3]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FNMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FADD.S {
encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
F[rd]f <= F[rs1]f + F[rs2]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
// F[rd]f <= F[rs1]f + F[rs2]f;
val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= (-1<<31);
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSUB.S {
encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
F[rd]f <= F[rs1]f - F[rs2]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
// F[rd]f <= F[rs1]f - F[rs2]f;
val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMUL.S {
encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
F[rd]f <= F[rs1]f * F[rs2];
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
// F[rd]f <= F[rs1]f * F[rs2]f;
val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FDIV.S {
encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
F[rd]f <= F[rs1]f / F[rs2]f;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
// F[rd]f <= F[rs1]f / F[rs2]f;
val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSQRT.S {
encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
F[rd]f<=sqrt(F[rs1]f);
args_disass:"x%rd$d, f%rs1$d";
//F[rd]f<=sqrt(F[rs1]f);
val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FSGNJ.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
}
FSGNJN.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
}
FSGNJX.S {
encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
}
FMIN.S {
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FMAX.S {
encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.W.S {
encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d";
X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCVT.WU.S {
encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
}
FMV.X.W {
encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d";
X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FEQ.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLT.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FLE.S {
encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
val flags[32] <= fdispatch_fget_flags();
FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
}
FCLASS.S {
encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d";
X[rd]<=fdispatch_fclass_s(F[rs1]{32});
}
FCVT.S.W {
encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f%rd$d, x%rs1$d";
val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
}
FCVT.S.WU {
encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f%rd$d, x%rs1$d";
val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
if(FLEN==32)
F[rd] <= res;
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | res;
}
}
FMV.X.W {
encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"x%rd$d, f%rs1$d";
X[rd]<=sext(F[rs1]{32});
}
FMV.W.X {
encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
args_disass:"f%rd$d, x%rs1$d";
if(FLEN==32)
F[rd] <= X[rs1];
else {
val upper[FLEN] <= -1<<31;
F[rd] <= upper*2 | X[rs1];
}
}
}
}

28
riscv/gen_input/RV32M.core_desc
View File

@ -41,9 +41,17 @@ InsructionSet RV32M extends RV32IBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
if(X[rs2]!=0)
X[rd] <= sext(X[rs1], 32) / sext(X[rs2], 32);
else
if(X[rs2]!=0){
val M1[XLEN] <= -1;
val MMIN[XLEN] <= -1<<(XLEN-1);
if(X[rs1]s==MMIN's)
if(X[rs2]s==M1's)
X[rd]<=MMIN;
else
X[rd] <= X[rs1]s / X[rs2]s;
else
X[rd] <= X[rs1]s / X[rs2]s;
}else
X[rd] <= -1;
}
}
@ -61,9 +69,17 @@ InsructionSet RV32M extends RV32IBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
if(X[rs2]!=0)
X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
else
if(X[rs2]!=0) {
val M1[XLEN] <= -1;
val MMIN[XLEN] <= -1<<(XLEN-1);
if(X[rs1]s==MMIN's)
if(X[rs2]s==M1's)
X[rd] <= 0;
else
X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
else
X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
} else
X[rd] <= X[rs1];
}
}

22
riscv/gen_input/minres_rv.core_desc
View File

@ -2,12 +2,13 @@ import "RV32IBase.core_desc"
import "RV32M.core_desc"
import "RV32A.core_desc"
import "RV32C.core_desc"
import "RV32F.core_desc"
import "RV64IBase.core_desc"
//import "RV64M.core_desc"
import "RV64A.core_desc"
Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
template:"vm_riscv.in.cpp";
constants {
XLEN:=32;
@ -25,6 +26,25 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
}
}
Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC {
constants {
XLEN:=32;
FLEN:=32;
XLEN2:=64;
XLEN_BIT_MASK:=0x1f;
PCLEN:=32;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000001;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
FFLAG_MASK:=0x1f;
}
}
Core RV64IA provides RV64IBase, RV64A, RV32A {
template:"vm_riscv.in.cpp";

17
riscv/gen_input/templates/incl-CORENAME.h.gtl
View File

@ -100,6 +100,8 @@ struct traits<${coreDef.name.toLowerCase()}> {
enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
constexpr static bool has_fp_regs = ${allRegs.find {it.name=='FCSR'}!= null ?'true':'false'};
};
struct ${coreDef.name.toLowerCase()}: public arch_if {
@ -112,8 +114,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
${coreDef.name.toLowerCase()}();
~${coreDef.name.toLowerCase()}();
const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
@ -158,9 +158,16 @@ protected:
} reg;
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;
<%
def fcsr = allRegs.find {it.name=='FCSR'}
if(fcsr != null) {%>
uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
<%} else { %>
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}
<%}%>
};
}

5
riscv/gen_input/templates/src-CORENAME.cpp.gtl
View File

@ -68,6 +68,7 @@ uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
return phys_addr_t(pc); // change logical address to physical address
}

26
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl
View File

@ -48,6 +48,12 @@
#include <array>
namespace iss {
namespace vm {
namespace fp_impl{
void add_fp_functions_2_module(llvm::Module *mod);
}
}
namespace ${coreDef.name.toLowerCase()} {
using namespace iss::arch;
using namespace llvm;
@ -81,6 +87,11 @@ protected:
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
}
void setup_module(llvm::Module* m) override {
super::setup_module(m);
vm::fp_impl::add_fp_functions_2_module(m);
}
inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
unsigned size) const {
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
@ -106,6 +117,10 @@ protected:
return this->builder.CreateLoad(get_reg_ptr(i), false);
}
llvm::Value* gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args);
llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*);
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
this->get_type(traits<ARCH>::XLEN));
@ -310,7 +325,16 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
bb, this->trap_blk, 1);
}
} // namespace ${coreDef.name.toLowerCase()}
template<typename ARCH>
inline llvm::Value* vm_impl<ARCH>::gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args) {
return this->builder.CreateCall(this->mod->getFunction(fname), args);
}
template<typename ARCH>
inline llvm::Value* vm_impl<ARCH>::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) {
}
} // namespace rv32imacf
template <>
std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {