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Added SystemC version of HiFive FE310

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This commit is contained in:
Eyck Jentzsch
2017-10-04 10:31:11 +02:00
parent d8184abbcc
commit 4867cca187
43 changed files with 1632 additions and 537 deletions
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158
riscv.sc/gen_input/aon.rdl Normal file
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@ -0,0 +1,158 @@
regfile aon_regs {
// Watchdog Timer Registers
reg {
name = "wdogcfg";
desc = "Watchdog Timer Config Register";
field {
name="data";
} data[31:0];
} wdogcfg @0x00;
reg {
name ="wdogcount";
desc = "Watchdog Timer Count Registers";
field {
name="data";
} data[31:0];
} wdogcount @0x08;
reg {
name ="wdogs";
desc = "";
field {
name="data";
} data[31:0];
} wdogs @0x10;
reg {
name ="wdogfeed";
desc = "";
field {
name="data";
} data[31:0];
} wdogfeed @0x18;
reg {
name ="wdogkey";
desc = "";
field {
name="data";
} data[31:0];
} wdogkey @0x1C;
reg {
name ="wdogcmp";
desc = "";
field {
name="data";
} data[31:0];
} wdogcmp @0x20;
// Real-Time Clock Registers
reg {
name ="rtccfg";
desc = "";
field {
name="data";
} data[31:0];
} rtccfg @0x40;
reg {
name ="rtclo";
desc = "";
field {
name="data";
} data[31:0];
} rtclo @0x48;
reg {
name ="rtchi";
desc = "";
field {
name="data";
} data[31:0];
} rtchi @0x4C;
reg {
name ="rtcs";
desc = "";
field {
name="data";
} data[31:0];
} rtcs @0x50;
reg {
name ="rtccmp";
desc = "";
field {
name="data";
} data[31:0];
} rtccmp @0x60;
// AON Clock Configuration Registers
reg {
name ="lfrosccfg";
desc = "";
field {
name="data";
} data[31:0];
} lfrosccfg @0x70;
// Backup Registers
reg {
name ="lfrosccfg";
desc = "";
field {
name="data";
} data[31:0];
} backup[32] @0x80;
// Power Management Unit
reg {
name ="pmuwakeupi";
desc = "";
field {
name="delay";
} delay[3:0];
field {
name="vddpaden";
} vddpaden[5:5];
field {
name="corerst";
} corerst[7:7];
field {
name="hfclkrst";
} hfclkrst[8:8];
} pmuwakeupi[8] @0x0100;
reg {
name ="pmusleepi";
desc = "";
field {
name="delay";
} delay[3:0];
field {
name="vddpaden";
} vddpaden[5:5];
field {
name="corerst";
} corerst[7:7];
field {
name="hfclkrst";
} hfclkrst[8:8];
} pmusleepi[8] @0x0120;
reg {
name ="pmuie";
desc = "";
field {
name="data";
} data[31:0];
} pmuie @0x0140;
reg {
name ="pmucause";
desc = "";
field {
name="data";
} data[31:0];
} pmucause @0x0144;
reg {
name ="pmusleep";
desc = "";
field {
name="data";
} data[31:0];
} pmusleep @0x0148;
reg {
name ="pmukey";
desc = "";
field {
name="data";
} data[31:0];
} pmukey @0x014C;
};

27
riscv.sc/gen_input/clint.rdl Normal file
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regfile clint_regs {
reg {
name = "msip";
desc = "Hart 0 software interrupt register";
field {
name="msip";
} msip[0:0];
} msip @0;
reg {
name = "mtimecmp";
desc = "Hart 0 time comparator register";
regwidth=64;
field {
name="data";
fieldwidth=64;
} data = 64'h7FFFFFFFFFFFFFFF;
} mtimecmp @0x4000;
reg {
name = "mtime";
desc = "Timer register";
regwidth=64;
field {
fieldwidth=64;
name="data";
} data[63:0];
} mtime @0xBFF8;
};

16
riscv.sc/gen_input/fe310.rdl
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@ -2,10 +2,18 @@
`include "uart.rdl"
`include "spi.rdl"
`include "plic.rdl"
`include "aon.rdl"
`include "prci.rdl"
`include "clint.rdl"
addrmap e300_plat_t {
plic_regs plic @0x0C000000;
gpio_regs gpio @0x10012000;
uart_regs uart @0x10013000;
spi_regs spi @0x10014000;
lsb0;
clint_regs clint @0x02000000;
plic_regs plic @0x0C000000;
aon_regs aon @0x10000000;
prci_regs prci @0x10008000;
gpio_regs gpio @0x10012000;
uart_regs uart0 @0x10013000;
uart_regs uart1 @0x10023000;
spi_regs spi @0x10014000;
} e300_plat;

1
riscv.sc/gen_input/gpio.rdl
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@ -1,5 +1,4 @@
regfile gpio_regs {
lsb0;
reg {
name="value";
desc="pin value";

20
riscv.sc/gen_input/plic.rdl
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@ -2,36 +2,26 @@ regfile plic_regs {
reg {
name="priority";
desc="interrupt source priority";
field {
name = "priority";
} priority[2:0];
field {} priority[2:0];
} priority[255] @0x004;
reg {
name="pending";
desc="pending irq";
field {
name = "pending";
} pending[31:0];
field {} pending[31:0];
} pending @0x1000;
reg {
name="enabled";
desc="enabled interrupts";
field {
name = "enabled";
} enabled[31:0];
field {} enabled[31:0];
} enabled @0x2000;
reg {
name="threshold";
desc="interrupt priority threshold";
field {
name = "threshold";
} \threshold[2:0];
field {} \threshold[2:0];
} \threshold @0x200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
field {
name = "interrupt_claimed";
} interrupt_claimed[31:0];
field {} interrupt_claimed[31:0];
} claim_complete @0x200004;
};

41
riscv.sc/gen_input/prci.rdl Normal file
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@ -0,0 +1,41 @@
regfile prci_regs {
reg {
name ="hfrosccfg";
desc = "";
field {} hfroscdiv[5:0];
field {} hfrosctrim[20:16];
field {} hfroscen[30:30];
field {} hfroscrdy[31:31];
} hfrosccfg @0x00;
reg {
name ="hfxosccfg";
desc = "";
field {} hfxoscrdy[31:31];
field {} hfxoscen[30:30];
} hfxosccfg @0x04;
reg {
name ="pllcfg";
desc = "";
field {} pllr[2:0];
field {} pllf[9:4];
field {} pllq[11:10];
field {} pllsel[16:16];
field {} pllrefsel[17:17];
field {} pllbypass[18:18];
field {} plllock[31:31];
} pllcfg @0x08;
reg {
name ="plloutdiv";
desc = "";
field {
name="data";
} data[31:0];
} plloutdiv @0x0c;
reg {
name ="coreclkcfg";
desc = "";
field {
name="data";
} data[31:0];
} coreclkcfg @0x10;
};

1
riscv.sc/gen_input/spi.rdl
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@ -1,5 +1,4 @@
regfile spi_regs {
lsb0;
reg {
name="sckdiv";
desc="Serial clock divisor";

63
riscv.sc/gen_input/uart.rdl
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@ -1,80 +1,45 @@
regfile uart_regs {
lsb0;
reg {
name="txdata";
desc="Transmit data register";
field {
name ="data";
} data[7:0];
field {
name ="full";
} full[31:31];
field {} data[7:0];
field {} full[31:31];
} txdata @0x00;
reg {
name="rxdata";
desc="Receive data register";
field {
name ="data";
} data[7:0];
field {
name ="empty";
} empty[31:31];
field {} data[7:0];
field {} empty[31:31];
}rxdata @0x04;
reg {
name="txctrl";
desc="Transmit control register";
field {
name ="txen";
} txen[1];
field {
name ="nstop";
} nstop[1];
field {
name ="reserved";
} reserved[14];
field {
name ="txcnt";
} txcnt[3];
field {} txen[1];
field {} nstop[1];
field {} txcnt[18:16];
}txctrl @0x08;
reg {
name="rxctrl";
desc="Receive control register";
field {
name ="rxen";
} rxen[1];
field {
name ="reserved";
} reserved[15];
field {
name ="rxcnt";
} rxcnt[3];
field {} rxen[1];
field {} rxcnt[18:16];
}rxctrl @0x0C;
reg {
name="ie";
desc="UART interrupt enable";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
field{} txwm[1];
field{} rxwm[1];
}ie @0x10;
reg {
name="ip";
desc="UART Interrupt pending";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
field{} txwm[1];
field{} rxwm[1];
} ip @0x14;
reg {
name="div";
desc="Baud rate divisor";
field{
name ="div";
} div[16];
field{} div[16];
} div @0x18;
};