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Adapted to log system

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This commit is contained in:
Eyck Jentzsch
2017-09-22 10:11:29 +02:00
parent 9a617dab57
commit 39150b68c0
18 changed files with 60 additions and 11394 deletions
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26
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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@ -40,7 +40,7 @@
#include <util/ities.h>
#include <util/sparse_array.h>
#include <elfio/elfio.hpp>
#include <util/logging.h>
#include <iss/log_categories.h>
#include <sstream>
#include <iomanip>
#include <unordered_map>
@ -628,9 +628,9 @@ template<typename BASE>
iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t& addr, unsigned length, uint8_t* const data){
#ifndef NDEBUG
if(addr.type& iss::DEBUG){
LOG(logging::DEBUG)<<"debug read of "<<length<<" bytes @addr "<<addr;
LOG(DEBUG)<<"debug read of "<<length<<" bytes @addr "<<addr;
} else {
LOG(logging::DEBUG)<<"read of "<<length<<" bytes @addr "<<addr;
LOG(DEBUG)<<"read of "<<length<<" bytes @addr "<<addr;
}
#endif
switch(addr.space){
@ -726,19 +726,19 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t& addr, unsigned len
const char* prefix = addr.type & iss::DEBUG?"debug ":"";
switch(length){
case 8:
LOG(logging::DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint64_t*)&data[0]<<std::dec<<") @addr "<<addr;
LOG(DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint64_t*)&data[0]<<std::dec<<") @addr "<<addr;
break;
case 4:
LOG(logging::DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint32_t*)&data[0]<<std::dec<<") @addr "<<addr;
LOG(DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint32_t*)&data[0]<<std::dec<<") @addr "<<addr;
break;
case 2:
LOG(logging::DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint16_t*)&data[0]<<std::dec<<") @addr "<<addr;
LOG(DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<*(uint16_t*)&data[0]<<std::dec<<") @addr "<<addr;
break;
case 1:
LOG(logging::DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<(uint16_t)data[0]<<std::dec<<") @addr "<<addr;
LOG(DEBUG)<<prefix<<"write of "<<length<<" bytes (0x"<<std::hex<<(uint16_t)data[0]<<std::dec<<") @addr "<<addr;
break;
default:
LOG(logging::DEBUG)<<prefix<<"write of "<<length<<" bytes @addr "<<addr;
LOG(DEBUG)<<prefix<<"write of "<<length<<" bytes @addr "<<addr;
}
#endif
try {
@ -965,14 +965,14 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t addr, unsigned length
switch(hostvar>>48){
case 0:
if(hostvar!=0x1)
LOG(logging::FATAL)<<"tohost value is 0x"<<std::hex<<hostvar<<std::dec<<" ("<<hostvar<<"), stopping simulation";
LOG(FATAL)<<"tohost value is 0x"<<std::hex<<hostvar<<std::dec<<" ("<<hostvar<<"), stopping simulation";
else
LOG(logging::INFO)<<"tohost value is 0x"<<std::hex<<hostvar<<std::dec<<" ("<<hostvar<<"), stopping simulation";
LOG(INFO)<<"tohost value is 0x"<<std::hex<<hostvar<<std::dec<<" ("<<hostvar<<"), stopping simulation";
throw(iss::simulation_stopped(hostvar));
case 0x0101:{
char c = static_cast<char>(hostvar & 0xff);
if(c=='\n' || c==0){
LOG(logging::INFO)<<"tohost send '"<<uart_buf.str()<<"'";
LOG(INFO)<<"tohost send '"<<uart_buf.str()<<"'";
uart_buf.str("");
} else
uart_buf<<c;
@ -1190,7 +1190,7 @@ uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
this->reg.trap_state=0;
char buffer[32];
sprintf(buffer, "0x%016lx", addr);
CLOG(logging::INFO, "disass")<<(trap_id?"Interrupt ":"Trap ")<<trap_id<<" with cause '"<<irq_str[cause]<<"' at address "<<buffer
CLOG(INFO, disass)<<(trap_id?"Interrupt ":"Trap ")<<trap_id<<" with cause '"<<irq_str[cause]<<"' at address "<<buffer
<<" occurred, changing privilege level from "<<lvl[cur_priv]<<" to "<<lvl[new_priv];
return this->reg.NEXT_PC;
}
@ -1230,7 +1230,7 @@ uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t flags) {
status|= pie<<inst_priv; // and set the pie
csr[mstatus]=status;
this->reg.machine_state=ppl;
CLOG(logging::INFO, "disass")<<"Executing xRET , changing privilege level from "<<lvl[cur_priv]<<" to "<<lvl[ppl];
CLOG(INFO, disass)<<"Executing xRET , changing privilege level from "<<lvl[cur_priv]<<" to "<<lvl[ppl];
return this->reg.NEXT_PC;
}