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Added cycle estimator and remove deprecated functions

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This commit is contained in:
Eyck Jentzsch
2018-03-30 17:59:40 +02:00
parent a690981957
commit 38471b8193
14 changed files with 280 additions and 53 deletions
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52
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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@ -35,12 +35,13 @@
#ifndef _RISCV_CORE_H_
#define _RISCV_CORE_H_
#include "iss/arch/traits.h"
#include "iss/arch_if.h"
#include "iss/log_categories.h"
#include "iss/vm_if.h"
#include "iss/instrumentation_if.h"
#include <elfio/elfio.hpp>
#include <iomanip>
#include <iss/arch/traits.h>
#include <iss/arch_if.h>
#include <iss/log_categories.h>
#include <iss/vm_if.h>
#include <sstream>
#include <unordered_map>
#include <util/ities.h>
@ -463,6 +464,7 @@ public:
virtual uint64_t leave_trap(uint64_t flags) override;
void wait_until(uint64_t flags) override;
void disass_output(uint64_t pc, const std::string instr) override {
std::stringstream s;
s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
@ -470,26 +472,54 @@ public:
CLOG(INFO, disass) << "0x"<<std::setw(16)<<std::setfill('0')<<std::hex<<pc<<"\t\t"<<instr<<"\t"<<s.str();
};
iss::instrumentation_if* get_instrumentation_if() override {return &instr_if;}
protected:
struct riscv_instrumentation_if : public iss::instrumentation_if{
riscv_instrumentation_if(riscv_hart_msu_vp<BASE>& arch):arch(arch){}
/**
* get the name of this architecture
*
* @return the name of this architecture
*/
const std::string core_type_name() const override {return traits<BASE>::core_type;}
virtual uint64_t get_pc(){ return arch.get_pc(); };
virtual uint64_t get_next_pc(){ return arch.get_next_pc(); };
virtual void set_curr_instr_cycles(unsigned cycles){ arch.cycle_offset+=cycles-1; };
riscv_hart_msu_vp<BASE>& arch;
};
friend struct riscv_instrumentation_if;
addr_t get_pc(){return this->reg.PC;}
addr_t get_next_pc(){return this->reg.NEXT_PC;}
virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data);
virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data);
virtual iss::status read_csr(unsigned addr, reg_t &val);
virtual iss::status write_csr(unsigned addr, reg_t val);
hart_state<reg_t> state;
uint64_t cycle_offset;
reg_t fault_data;
std::array<vm_info,2> vm;
uint64_t tohost = tohost_dflt;
uint64_t fromhost = fromhost_dflt;
unsigned to_host_wr_cnt = 0;
riscv_instrumentation_if instr_if;
reg_t fault_data;
using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
using csr_page_type = typename csr_type::page_type;
mem_type mem;
csr_type csr;
hart_state<reg_t> state;
std::array<vm_info,2> vm;
void update_vm_info();
unsigned to_host_wr_cnt = 0;
std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation;
@ -513,7 +543,7 @@ protected:
template <typename BASE>
riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
: state() {
: state(), cycle_offset(0), instr_if(*this) {
csr[misa] = hart_state<reg_t>::get_misa();
uart_buf.str("");
// read-only registers
@ -814,7 +844,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
auto cycle_val= this->reg.icount + cycle_offset;
if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val);
} else if (addr == mcycleh) {
@ -825,7 +855,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigne
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
uint64_t time_val=(this->reg.icount + cycle_offset) / (100000000/32768-1); //-> ~3052;
if (addr == time) {
val = static_cast<reg_t>(time_val);
} else if (addr == timeh) {

4
riscv/incl/iss/arch/rv32imac.h
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@ -130,8 +130,6 @@ struct rv32imac: public arch_if {
rv32imac();
~rv32imac();
const std::string core_type_name() const override {return traits<rv32imac>::core_type;}
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
@ -201,8 +199,6 @@ protected:
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;
};
}

4
riscv/incl/iss/arch/rv64ia.h
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@ -130,8 +130,6 @@ struct rv64ia: public arch_if {
rv64ia();
~rv64ia();
const std::string core_type_name() const override {return traits<rv64ia>::core_type;}
void reset(uint64_t address=0) override;
uint8_t* get_regs_base_ptr() override;
@ -201,8 +199,6 @@ protected:
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;
};
}

12
riscv/incl/iss/debugger/riscv_target_adapter.h
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@ -205,7 +205,7 @@ status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std
// auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
// arch::traits<ARCH>::reg_e>(reg_no))/8;
auto *reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)) / 8;
auto reg_width = arch::traits<ARCH>::reg_bit_width(reg_no) / 8;
data.resize(reg_width);
avail.resize(reg_width);
auto offset = traits<ARCH>::reg_byte_offset(reg_no);
@ -319,12 +319,14 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int typ
template <typename ARCH> status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
std::function<void(unsigned)> stop_callback) {
unsigned reg_no = arch::traits<ARCH>::PC;
std::vector<uint8_t> data(8);
*(reinterpret_cast<uint64_t *>(&data[0])) = addr;
core->set_reg(reg_no, data);
auto* reg_base = core->get_regs_base_ptr();
auto reg_width = arch::traits<ARCH>::reg_bit_width(arch::traits<ARCH>::PC) / 8;
auto offset = traits<ARCH>::reg_byte_offset(arch::traits<ARCH>::PC);
const uint8_t* iter = reinterpret_cast<const uint8_t*>(&addr);
std::copy(iter, iter + reg_width, reg_base);
return resume_from_current(step, sig, thread, stop_callback);
}
template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string& out_buf) {
const std::string res{
"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"

96
riscv/incl/iss/plugin/cycle_estimate.h Normal file
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@ -0,0 +1,96 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial API and implementation
******************************************************************************/
#ifndef _ISS_PLUGIN_CYCLE_ESTIMATE_H_
#define _ISS_PLUGIN_CYCLE_ESTIMATE_H_
#include "iss/vm_plugin.h"
#include "iss/instrumentation_if.h"
#include <json/json.h>
#include <string>
#include <unordered_map>
namespace iss {
namespace plugin {
class cycle_estimate: public iss::vm_plugin {
BEGIN_BF_DECL(instr_desc, uint32_t)
BF_FIELD(taken, 24, 8)
BF_FIELD(not_taken, 16, 8)
BF_FIELD(size, 0, 16)
instr_desc(uint32_t size, uint32_t taken, uint32_t not_taken): instr_desc() {
this->size=size;
this->taken=taken;
this->not_taken=not_taken;
}
END_BF_DECL();
public:
cycle_estimate() = delete;
cycle_estimate(const cycle_estimate& ) = delete;
cycle_estimate(const cycle_estimate&&) = delete;
cycle_estimate(std::string config_file_name);
virtual ~cycle_estimate();
cycle_estimate& operator=(const cycle_estimate& ) = delete;
cycle_estimate& operator=(const cycle_estimate&& ) = delete;
bool registration(const char* const version, vm_if& arch) override;
sync_type get_sync() override {return POST_SYNC;};
void callback(instr_info_t instr_info) override;
private:
iss::instrumentation_if* arch_instr;
std::vector<instr_desc> delays;
struct pair_hash {
size_t operator()(const std::pair<uint64_t, uint64_t>& p) const{
std::hash<uint64_t> hash;
return hash(p.first)+hash(p.second);
}
};
std::unordered_map<std::pair<uint64_t, uint64_t>, uint64_t, pair_hash> blocks;
Json::Value root;
};
}
}
#endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */

16
riscv/incl/iss/plugin/instruction_count.h
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@ -32,8 +32,8 @@
* eyck@minres.com - initial API and implementation
******************************************************************************/
#ifndef _ISS_PLUGIN_CYCLE_COUNTER_H_
#define _ISS_PLUGIN_CYCLE_COUNTER_H_
#ifndef _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
#define _ISS_PLUGIN_INSTRUCTION_COUNTER_H_
#include <iss/vm_plugin.h>
#include <json/json.h>
@ -52,15 +52,23 @@ class instruction_count: public iss::vm_plugin {
public:
instruction_count() = delete;
instruction_count(const instruction_count& ) = delete;
instruction_count(const instruction_count&&) = delete;
instruction_count(std::string config_file_name);
virtual ~instruction_count();
instruction_count& operator=(const instruction_count& ) = delete;
instruction_count& operator=(const instruction_count&& ) = delete;
bool registration(const char* const version, vm_if& arch) override;
sync_type get_sync() override {return POST_SYNC;};
void callback(unsigned core_id, unsigned cluster_id, sync_type phase, unsigned instr_id) override;
void callback(instr_info_t instr_info) override;
private:
Json::Value root;
std::vector<instr_delay> delays;
@ -70,4 +78,4 @@ private:
}
}
#endif /* _ISS_PLUGIN_CYCLE_COUNTER_H_ */
#endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */