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Cleanup of SC wrapper

This commit is contained in:
Eyck Jentzsch 2018-04-24 19:03:30 +02:00
parent cff4b1d33b
commit 292e2dbb89
2 changed files with 10 additions and 10 deletions
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2
dbt-core

@ -1 +1 @@
Subproject commit d9512853b22e869938013c8dc0c6678a92d52c0e Subproject commit 555bff0a20cfbf775994ed74b188b9af480df883

18
riscv.sc/src/sysc/core_complex.cpp
View File

@ -103,7 +103,9 @@ public:
base_type::hart_state<base_type::reg_t>& get_state() { return this->state; } base_type::hart_state<base_type::reg_t>& get_state() { return this->state; }
void notify_phase(exec_phase) override; void notify_phase(exec_phase p) override {
if(p == ISTART) owner->sync(this->reg.icount+cycle_offset);
}
sync_type needed_sync() const override { return PRE_SYNC; } sync_type needed_sync() const override { return PRE_SYNC; }
@ -131,9 +133,12 @@ public:
return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err; return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
else{ else{
auto res = owner->write_mem(addr.val, length, data) ? Ok : Err; auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
// TODO: this is an ugly hack (clear MTIP on mtimecmp write), needs to be fixed // clear MTIP on mtimecmp write
if(addr.val==0x2004000) if(addr.val==0x2004000){
this->csr[arch::mip] &= ~(1ULL<<7); reg_t val;
this->read_csr(arch::mip, val);
this->write_csr(arch::mip, val & ~(1ULL<<7));
}
return res; return res;
} }
} }
@ -198,11 +203,6 @@ int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func
} }
void core_wrapper::notify_phase(exec_phase p) {
if(p == ISTART)
owner->sync(this->reg.icount+cycle_offset);
}
core_complex::core_complex(sc_core::sc_module_name name) core_complex::core_complex(sc_core::sc_module_name name)
: sc_core::sc_module(name) : sc_core::sc_module(name)
, NAMED(initiator) , NAMED(initiator)