Renamed hart name and core wrapper name

riscv/src/iss/rv32imac.cpp

@@ -28,15 +28,16 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Contributors:
-//       eyck@minres.com - initial API and implementation
+// Created on: Tue Aug 29 16:45:20 CEST 2017
+//             *      rv32imac.cpp Author: <CoreDSL Generator>
+//
 ////////////////////////////////////////////////////////////////////////////////
 
 #include "util/ities.h"
 #include <easylogging++.h>
 
 #include <elfio/elfio.hpp>
-#include <iss/arch/minrv_ima.h>
+#include <iss/arch/rv32imac.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -51,25 +52,25 @@ extern "C" {
 
 using namespace iss::arch;
 
-minrv_ima::minrv_ima() {
+rv32imac::rv32imac() {
     reg.icount=0;
 }
 
-minrv_ima::~minrv_ima(){
+rv32imac::~rv32imac(){
 }
 
-void minrv_ima::reset(uint64_t address) {
-    for(size_t i=0; i<traits<minrv_ima>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<minrv_ima>::reg_t),0));
+void rv32imac::reset(uint64_t address) {
+    for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
     reg.machine_state=0x3;
 }
 
-uint8_t* minrv_ima::get_regs_base_ptr(){
+uint8_t* rv32imac::get_regs_base_ptr(){
     return reinterpret_cast<uint8_t*>(&reg);
 }
 
-minrv_ima::phys_addr_t minrv_ima::v2p(const iss::addr_t& pc) {
+rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
     return phys_addr_t(pc); //change logical address to physical address
 }