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Renamed hart name and core wrapper name

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This commit is contained in:
Eyck Jentzsch
2017-08-29 16:56:11 +02:00
parent 9619de45d0
commit 1cb492b594
9 changed files with 104 additions and 103 deletions
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4
riscv/src/CMakeLists.txt
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@ -2,8 +2,8 @@
FILE(GLOB RiscVHeaders *.h)
set(LIB_HEADERS ${RiscVHeaders} )
set(LIB_SOURCES
iss/minrv_ima.cpp
internal/vm_minrv_ima.cpp
iss/rv32imac.cpp
internal/vm_rv32imac.cpp
)
set(APP_HEADERS )

6
riscv/src/internal/vm_riscv.in.cpp
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@ -42,10 +42,10 @@
#include "iss/vm_base.h"
#include "iss/arch/CORE_DEF_NAME.h"
#include "iss/arch/riscv_core.h"
#include "iss/debugger/server.h"
#include <boost/format.hpp>
#include "../../incl/iss/arch/riscv_hart_msu_vp.h"
namespace iss {
namespace CORE_DEF_NAME {
@ -452,13 +452,13 @@ template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port,
return ret;\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
}
CREATE_FUNCS(arch::CORE_DEF_NAME)

22
riscv/src/internal/vm_minrv_ima.cpp → riscv/src/internal/vm_rv32imac.cpp
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@ -41,14 +41,14 @@
#include <cstring>
#include "iss/vm_base.h"
#include "iss/arch/minrv_ima.h"
#include "iss/arch/riscv_core.h"
#include "iss/arch/rv32imac.h"
#include "iss/debugger/server.h"
#include <boost/format.hpp>
#include "../../incl/iss/arch/riscv_hart_msu_vp.h"
namespace iss {
namespace minrv_ima {
namespace rv32imac {
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
@ -5521,27 +5521,27 @@ void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
this->trap_blk, 1);
}
} // namespace minrv_ima
} // namespace rv32imac
#define CREATE_FUNCS(ARCH) \
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
std::unique_ptr<minrv_ima::vm_impl<ARCH> > ret = std::make_unique<minrv_ima::vm_impl<ARCH> >(*core, dump);\
std::unique_ptr<rv32imac::vm_impl<ARCH> > ret = std::make_unique<rv32imac::vm_impl<ARCH> >(*core, dump);\
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
return ret;\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
return std::make_unique<minrv_ima::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
return std::make_unique<rv32imac::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
}
CREATE_FUNCS(arch::minrv_ima)
CREATE_FUNCS(arch::rv32imac)
namespace minrv_ima {
namespace rv32imac {
template<typename ARCH>
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
@ -5758,5 +5758,5 @@ namespace minrv_ima {
vm->get_arch()->set_reg(reg_no, data);
return resume_from_current(step, sig);
}
} // namespace minrv_ima
} // namespace rv32imac
} // namespace iss

19
riscv/src/iss/minrv_ima.cpp → riscv/src/iss/rv32imac.cpp
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@ -28,15 +28,16 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
// Created on: Tue Aug 29 16:45:20 CEST 2017
// * rv32imac.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#include "util/ities.h"
#include <easylogging++.h>
#include <elfio/elfio.hpp>
#include <iss/arch/minrv_ima.h>
#include <iss/arch/rv32imac.h>
#ifdef __cplusplus
extern "C" {
@ -51,25 +52,25 @@ extern "C" {
using namespace iss::arch;
minrv_ima::minrv_ima() {
rv32imac::rv32imac() {
reg.icount=0;
}
minrv_ima::~minrv_ima(){
rv32imac::~rv32imac(){
}
void minrv_ima::reset(uint64_t address) {
for(size_t i=0; i<traits<minrv_ima>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<minrv_ima>::reg_t),0));
void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
}
uint8_t* minrv_ima::get_regs_base_ptr(){
uint8_t* rv32imac::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
minrv_ima::phys_addr_t minrv_ima::v2p(const iss::addr_t& pc) {
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
}

8
riscv/src/main.cpp
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@ -37,7 +37,7 @@
#include <iss/iss.h>
#include <iostream>
#include <iss/arch/minrv_ima.h>
#include <iss/arch/rv32imac.h>
#ifndef WITHOUT_LLVM
#include <iss/jit/MCJIThelper.h>
#endif
@ -72,13 +72,13 @@ int main(int argc, char *argv[]) {
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = vm.count("gdb-port")?
iss::create<iss::arch::minrv_ima>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
iss::create<iss::arch::minrv_ima>("rv32ima", dump);
iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
iss::create<iss::arch::rv32imac>("rv32ima", dump);
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::minrv_ima>::MEM);
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
} //else
// LOG(FATAL)<<"At least one (flash-)input file (ELF or IHEX) needs to be specified";

2
riscv/src/minres_rv.core_desc
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@ -6,7 +6,7 @@ import "RV32C.core_desc"
//import "RV64M.core_desc"
//import "RV64A.core_desc"
Core MinRV_IMA provides RV32IBase,RV32M,RV32A, RV32CI {
Core RV32IMAC provides RV32IBase,RV32M,RV32A, RV32CI {
template:"vm_riscv.in.cpp";
constants {
XLEN:=32;