Renamed hart name and core wrapper name
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riscv/incl/iss/arch/rv32imac.h
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riscv/incl/iss/arch/rv32imac.h
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Tue Aug 29 16:45:20 CEST 2017
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// * rv32imac.h Author: <CoreDSL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _RV32IMAC_H_
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#define _RV32IMAC_H_
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#include <iss/arch_if.h>
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#include <iss/vm_if.h>
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#include <iss/arch/traits.h>
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namespace iss {
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namespace arch {
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struct rv32imac;
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template<>
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struct traits<rv32imac> {
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enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
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enum reg_e {
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X0,
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X1,
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X2,
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X3,
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X4,
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X5,
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X6,
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X7,
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X8,
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X9,
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X10,
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X11,
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X12,
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X13,
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X14,
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X15,
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X16,
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X17,
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X18,
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X19,
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X20,
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X21,
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X22,
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X23,
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X24,
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X25,
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X26,
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X27,
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X28,
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X29,
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X30,
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X31,
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PC,
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NUM_REGS,
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NEXT_PC=NUM_REGS,
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TRAP_STATE,
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PENDING_TRAP,
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MACHINE_STATE,
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ICOUNT
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};
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typedef uint32_t reg_t;
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typedef uint32_t addr_t;
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typedef uint32_t code_word_t; //TODO: check removal
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typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
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typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
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constexpr static unsigned reg_bit_width(unsigned r) {
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const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
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return RV32IMAC_reg_size[r];
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}
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constexpr static unsigned reg_byte_offset(unsigned r) {
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const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
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return RV32IMAC_reg_byte_offset[r];
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}
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enum sreg_flag_e {FLAGS};
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enum mem_type_e {MEM,CSR,FENCE,RES};
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};
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struct rv32imac: public arch_if {
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using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
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using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
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using reg_t = typename traits<rv32imac>::reg_t;
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using addr_t = typename traits<rv32imac>::addr_t;
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rv32imac();
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~rv32imac();
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virtual void reset(uint64_t address=0) override;
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virtual uint8_t* get_regs_base_ptr() override;
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/// deprecated
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virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
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virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
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/// deprecated
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virtual bool get_flag(int flag) override {return false;}
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virtual void set_flag(int, bool value) override {};
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/// deprecated
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virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
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virtual void notify_phase(exec_phase phase){
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if(phase==ISTART){
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++reg.icount;
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reg.PC=reg.NEXT_PC;
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}
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}
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uint64_t get_icount() { return reg.icount;}
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virtual phys_addr_t v2p(const iss::addr_t& pc);
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virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
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protected:
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struct RV32IMAC_regs {
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uint32_t X0;
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uint32_t X1;
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uint32_t X2;
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uint32_t X3;
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uint32_t X4;
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uint32_t X5;
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uint32_t X6;
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uint32_t X7;
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uint32_t X8;
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uint32_t X9;
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uint32_t X10;
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uint32_t X11;
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uint32_t X12;
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uint32_t X13;
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uint32_t X14;
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uint32_t X15;
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uint32_t X16;
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uint32_t X17;
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uint32_t X18;
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uint32_t X19;
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uint32_t X20;
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uint32_t X21;
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uint32_t X22;
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uint32_t X23;
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uint32_t X24;
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uint32_t X25;
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uint32_t X26;
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uint32_t X27;
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uint32_t X28;
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uint32_t X29;
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uint32_t X30;
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uint32_t X31;
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uint32_t PC;
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uint32_t NEXT_PC;
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uint32_t trap_state, pending_trap, machine_state;
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uint64_t icount;
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} reg;
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};
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}
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}
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#endif /* _RV32IMAC_H_ */
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