VP/HIFIVE1-VP
8
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Streamline arch descriptions according to latest CoreDSL changes

Browse Source
This commit is contained in:
Eyck Jentzsch
2018-04-24 17:18:24 +02:00
parent 65ceedd157
commit 142654b0a2
12 changed files with 73 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
riscv/incl/iss/arch/rv32gc.h
View File

@ -48,7 +48,7 @@ struct traits<rv32gc> {
constexpr static char const* const core_type = "RV32GC";
enum constants {XLEN=32, FLEN=64, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095, FFLAG_MASK=31};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095};
constexpr static unsigned FP_REGS_SIZE = 64;

2
riscv/incl/iss/arch/rv32imac.h
View File

@ -48,7 +48,7 @@ struct traits<rv32imac> {
constexpr static char const* const core_type = "RV32IMAC";
enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095};
constexpr static unsigned FP_REGS_SIZE = 0;

2
riscv/incl/iss/arch/rv64ia.h
View File

@ -48,7 +48,7 @@ struct traits<rv64ia> {
constexpr static char const* const core_type = "RV64IA";
enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
constexpr static unsigned FP_REGS_SIZE = 0;