Streamline arch descriptions according to latest CoreDSL changes

2018-04-24 17:18:24 +02:00
parent 65ceedd157
commit 142654b0a2
12 changed files with 73 additions and 55 deletions
--- a/riscv/gen_input/RV32D.core_desc
+++ b/riscv/gen_input/RV32D.core_desc
@@ -2,7 +2,7 @@ import "RV32IBase.core_desc"

 InsructionSet RV32D extends RV32IBase{
 	constants {
-		FLEN, FFLAG_MASK
+		FLEN, FFLAG_MASK := 0x1f
 	} 
 	registers {
 		[31:0]    F[FLEN],  FCSR[32]