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Streamline arch descriptions according to latest CoreDSL changes

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This commit is contained in:
Eyck Jentzsch
2018-04-24 17:18:24 +02:00
parent 65ceedd157
commit 142654b0a2
12 changed files with 73 additions and 55 deletions
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2
riscv/gen_input/RV32D.core_desc
View File

@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
InsructionSet RV32D extends RV32IBase{
constants {
FLEN, FFLAG_MASK
FLEN, FFLAG_MASK := 0x1f
}
registers {
[31:0] F[FLEN], FCSR[32]

2
riscv/gen_input/RV32F.core_desc
View File

@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
InsructionSet RV32F extends RV32IBase{
constants {
FLEN, FFLAG_MASK
FLEN, FFLAG_MASK := 0x1f
}
registers {
[31:0] F[FLEN], FCSR[32]

10
riscv/gen_input/RV32IBase.core_desc
View File

@ -1,12 +1,12 @@
InsructionSet RV32IBase {
constants {
XLEN,
XLEN_BIT_MASK,
PCLEN,
fence,
fencei,
fencevmal,
fencevmau
XLEN_BIT_MASK:=0x1f,
fence:=0,
fencei:=1,
fencevmal:=2,
fencevmau:=3
}
address_spaces {

10
riscv/gen_input/RV32M.core_desc
View File

@ -2,14 +2,14 @@ import "RV32IBase.core_desc"
InsructionSet RV32M extends RV32IBase {
constants {
XLEN2
MAXLEN:=128
}
instructions{
MUL{
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res , XLEN);
}
}
@ -17,7 +17,7 @@ InsructionSet RV32M extends RV32IBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2);
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -25,7 +25,7 @@ InsructionSet RV32M extends RV32IBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -33,7 +33,7 @@ InsructionSet RV32M extends RV32IBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
if(rd != 0){
val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}

26
riscv/gen_input/minres_rv.core_desc
View File

@ -13,15 +13,10 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
template:"vm_riscv.in.cpp";
constants {
XLEN:=32;
XLEN2:=64;
XLEN_BIT_MASK:=0x1f;
PCLEN:=32;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000001;
MISA_VAL:=0b01000000000101000001000100000101;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
}
@ -31,18 +26,12 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
constants {
XLEN:=32;
FLEN:=64;
XLEN2:=64;
XLEN_BIT_MASK:=0x1f;
PCLEN:=32;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000001;
MISA_VAL:=0b01000000000101000001000100101101;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
FFLAG_MASK:=0x1f;
}
}
@ -51,13 +40,8 @@ Core RV64IA provides RV64IBase, RV64A, RV32A {
template:"vm_riscv.in.cpp";
constants {
XLEN:=64;
XLEN2:=128;
XLEN_BIT_MASK:=0x3f;
PCLEN:=64;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b10000000000001000000000100000001;
PGSIZE := 4096; //1 << 12;