HIFIVE1-VP/riscv.sc/gen_input/fe310.rdl

`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "plic.rdl"
`include "aon.rdl"
`include "prci.rdl"
`include "clint.rdl"

addrmap e300_plat_t {
	lsb0;
	clint_regs clint @0x02000000;
    plic_regs  plic  @0x0C000000;
    aon_regs   aon   @0x10000000;
    prci_regs  prci  @0x10008000;
    gpio_regs  gpio  @0x10012000;
    uart_regs  uart0 @0x10013000;
    spi_regs   spi   @0x10014000;  
    uart_regs  uart1 @0x10023000;
} e300_plat;