2017-08-27 12:10:38 +02:00
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import "RV64IBase.core_desc"
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InsructionSet RV64M extends RV64IBase {
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2018-04-30 19:22:00 +02:00
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instructions{
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MULW{
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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X[rd]<= X[rs1] * X[rs2];
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}
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}
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DIVW {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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X[rd] <= X[rs1]s / X[rs2]s;
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}
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}
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DIVUW {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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X[rd] <= X[rs1] / X[rs2];
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}
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}
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REMW {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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X[rd] <= X[rs1]s % X[rs2]s;
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}
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}
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REMUW {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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X[rd] <= X[rs1] % X[rs2];
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}
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}
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}
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2017-08-27 12:10:38 +02:00
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}
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