2017-08-27 12:10:38 +02:00
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InsructionSet RV32IBase {
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2018-04-30 19:22:00 +02:00
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constants {
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XLEN,
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PCLEN,
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XLEN_BIT_MASK:=0x1f,
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2018-04-24 17:18:24 +02:00
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fence:=0,
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fencei:=1,
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fencevmal:=2,
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fencevmau:=3
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2018-04-30 19:22:00 +02:00
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}
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address_spaces {
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MEM[8], CSR[XLEN], FENCE[XLEN]
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}
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registers {
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[31:0] X[XLEN],
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PC[XLEN](is_pc),
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alias ZERO[XLEN] is X[0]
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}
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instructions {
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LUI{
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encoding: imm[31:12]s | rd[4:0] | b0110111;
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args_disass: "x%rd$d, 0x%imm$05x";
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if(rd!=0) X[rd] <= imm;
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}
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AUIPC{
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encoding: imm[31:12]s | rd[4:0] | b0010111;
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args_disass: "x%rd%, 0x%imm$08x";
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2018-05-09 12:14:59 +02:00
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if(rd!=0) X[rd] <= PC's+imm;
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2018-04-30 19:22:00 +02:00
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}
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JAL(no_cont){
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encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
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args_disass: "x%rd$d, 0x%imm$x";
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if(rd!=0) X[rd] <= PC+4;
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2018-05-09 12:14:59 +02:00
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PC<=PC's+imm;
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2018-04-30 19:22:00 +02:00
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}
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JALR(no_cont){
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
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args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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val new_pc[XLEN] <= X[rs1]'s+ imm;
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2017-11-23 14:48:18 +01:00
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val align[XLEN] <= new_pc & 0x2;
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2018-04-30 19:22:00 +02:00
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if(align != 0){
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raise(0, 0);
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} else {
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if(rd!=0) X[rd] <= PC+4;
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PC<=new_pc & ~0x1;
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}
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}
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BEQ(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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BNE(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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BLT(no_cont,cond){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]s<X[rs2]s, PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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BGE(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]s>=X[rs2]s, PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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BLTU(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]<X[rs2],PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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BGEU(no_cont,cond) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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2018-05-09 12:14:59 +02:00
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PC<=choose(X[rs1]>=X[rs2], PC's+imm, PC+4);
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2018-04-30 19:22:00 +02:00
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}
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LB {
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s+imm;
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2018-04-30 19:22:00 +02:00
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if(rd!=0) X[rd]<=sext(MEM[offs]);
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}
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LH {
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encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s+imm;
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2018-04-30 19:22:00 +02:00
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if(rd!=0) X[rd]<=sext(MEM[offs]{16});
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}
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LW {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s+imm;
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2018-04-30 19:22:00 +02:00
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if(rd!=0) X[rd]<=sext(MEM[offs]{32});
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}
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LBU {
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encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s+imm;
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2018-04-30 19:22:00 +02:00
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if(rd!=0) X[rd]<=zext(MEM[offs]);
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}
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LHU {
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encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s+imm;
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2018-04-30 19:22:00 +02:00
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if(rd!=0) X[rd]<=zext(MEM[offs]{16});
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}
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SB {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s + imm;
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2018-04-30 19:22:00 +02:00
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MEM[offs] <= X[rs2];
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}
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SH {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s + imm;
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2018-04-30 19:22:00 +02:00
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MEM[offs]{16} <= X[rs2];
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}
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SW {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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2018-05-09 12:14:59 +02:00
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val offs[XLEN] <= X[rs1]'s + imm;
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2018-04-30 19:22:00 +02:00
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MEM[offs]{32} <= X[rs2];
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}
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ADDI {
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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2018-05-09 12:14:59 +02:00
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if(rd != 0) X[rd] <= X[rs1]'s + imm;
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2018-04-30 19:22:00 +02:00
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}
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SLTI {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0);
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}
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SLTIU {
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encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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val full_imm[XLEN] <= imm's;
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if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
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}
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XORI {
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2018-11-08 13:31:28 +01:00
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encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
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2018-04-30 19:22:00 +02:00
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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2018-11-08 13:31:28 +01:00
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if(rd != 0) X[rd] <= X[rs1]s ^ imm;
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2018-04-30 19:22:00 +02:00
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}
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ORI {
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2018-11-08 13:31:28 +01:00
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encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
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2018-04-30 19:22:00 +02:00
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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2018-11-08 13:31:28 +01:00
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if(rd != 0) X[rd] <= X[rs1]s | imm;
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2018-04-30 19:22:00 +02:00
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}
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ANDI {
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2018-11-08 13:31:28 +01:00
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encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
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2018-04-30 19:22:00 +02:00
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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2018-11-08 13:31:28 +01:00
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if(rd != 0) X[rd] <= X[rs1]s & imm;
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2018-04-30 19:22:00 +02:00
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}
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SLLI {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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if(shamt > 31){
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raise(0,0);
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} else {
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if(rd != 0) X[rd] <= shll(X[rs1], shamt);
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}
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}
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SRLI {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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2017-11-23 14:48:18 +01:00
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if(shamt > 31){
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2018-02-06 12:34:34 +01:00
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raise(0,0);
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2017-11-23 14:48:18 +01:00
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} else {
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2018-04-30 19:22:00 +02:00
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if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
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}
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}
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SRAI {
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encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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if(shamt > 31){
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2018-02-06 12:34:34 +01:00
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raise(0,0);
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2017-11-23 14:48:18 +01:00
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} else {
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2018-04-30 19:22:00 +02:00
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if(rd != 0) X[rd] <= shra(X[rs1], shamt);
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}
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}
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ADD {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] + X[rs2];
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}
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SUB {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] - X[rs2];
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}
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SLL {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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SLT {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0);
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}
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SLTU {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0);
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}
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XOR {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] ^ X[rs2];
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}
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SRL {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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SRA {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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OR {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] | X[rs2];
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}
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AND {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] & X[rs2];
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}
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FENCE {
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encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111;
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FENCE[fence] <= pred<<4 | succ;
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}
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FENCE_I(flush) {
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encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ;
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FENCE[fencei] <= imm;
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}
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ECALL(no_cont) {
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|
|
|
encoding: b000000000000 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
raise(0, 11);
|
|
|
|
}
|
|
|
|
EBREAK(no_cont) {
|
|
|
|
encoding: b000000000001 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
raise(0, 3);
|
|
|
|
}
|
|
|
|
URET(no_cont) {
|
|
|
|
encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
leave(0);
|
|
|
|
}
|
|
|
|
SRET(no_cont) {
|
|
|
|
encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
leave(1);
|
|
|
|
}
|
|
|
|
MRET(no_cont) {
|
|
|
|
encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
leave(3);
|
|
|
|
}
|
|
|
|
WFI {
|
|
|
|
encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011;
|
|
|
|
wait(1);
|
|
|
|
}
|
|
|
|
SFENCE.VMA {
|
|
|
|
encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011;
|
|
|
|
FENCE[fencevmal] <= rs1;
|
|
|
|
FENCE[fencevmau] <= rs2;
|
|
|
|
}
|
|
|
|
CSRRW {
|
|
|
|
encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
2017-08-27 12:10:38 +02:00
|
|
|
val rs_val[XLEN] <= X[rs1];
|
2018-04-30 19:22:00 +02:00
|
|
|
if(rd!=0){
|
|
|
|
val csr_val[XLEN] <= CSR[csr];
|
2017-08-27 12:10:38 +02:00
|
|
|
CSR[csr] <= rs_val;
|
|
|
|
// make sure Xrd is updated once CSR write succeeds
|
2018-04-30 19:22:00 +02:00
|
|
|
X[rd] <= csr_val;
|
|
|
|
} else {
|
|
|
|
CSR[csr] <= rs_val;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
CSRRS {
|
|
|
|
encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
|
|
|
val xrd[XLEN] <= CSR[csr];
|
|
|
|
val xrs1[XLEN] <= X[rs1];
|
|
|
|
if(rd!=0) X[rd] <= xrd;
|
|
|
|
if(rs1!=0) CSR[csr] <= xrd | xrs1;
|
|
|
|
}
|
|
|
|
CSRRC {
|
|
|
|
encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, x%rs1$d";
|
|
|
|
val xrd[XLEN] <= CSR[csr];
|
|
|
|
val xrs1[XLEN] <= X[rs1];
|
|
|
|
if(rd!=0) X[rd] <= xrd;
|
|
|
|
if(rs1!=0) CSR[csr] <= xrd & ~xrs1;
|
|
|
|
}
|
|
|
|
CSRRWI {
|
|
|
|
encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
|
|
|
if(rd!=0) X[rd] <= CSR[csr];
|
|
|
|
CSR[csr] <= zext(zimm);
|
|
|
|
}
|
|
|
|
CSRRSI {
|
|
|
|
encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
|
|
|
val res[XLEN] <= CSR[csr];
|
|
|
|
if(zimm!=0) CSR[csr] <= res | zext(zimm);
|
|
|
|
// make sure rd is written after csr write succeeds
|
|
|
|
if(rd!=0) X[rd] <= res;
|
|
|
|
}
|
|
|
|
CSRRCI {
|
|
|
|
encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011;
|
|
|
|
args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
|
|
|
|
val res[XLEN] <= CSR[csr];
|
2017-08-27 12:10:38 +02:00
|
|
|
if(rd!=0) X[rd] <= res;
|
2018-04-30 19:22:00 +02:00
|
|
|
if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN);
|
|
|
|
}
|
|
|
|
}
|
2017-08-27 12:10:38 +02:00
|
|
|
}
|
|
|
|
|