2018-11-08 13:31:28 +01:00
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/*******************************************************************************
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* Copyright (C) 2018 MINRES Technologies GmbH
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* All rights reserved.
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2018-07-12 15:27:36 +02:00
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*
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2018-11-08 13:31:28 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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2018-07-12 15:27:36 +02:00
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2019-07-16 15:54:15 +02:00
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#ifndef __SYSC_TOP_SYSTEM_H_
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#define __SYSC_TOP_SYSTEM_H_
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2018-07-12 15:27:36 +02:00
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2018-07-28 09:45:49 +02:00
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#include "dcmotor.h"
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#include "h_bridge.h"
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#include <memory>
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#include <systemc>
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#include "hifive1.h"
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namespace sysc {
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class system : sc_core::sc_module {
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public:
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SC_HAS_PROCESS(system);// NOLINT
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2018-07-13 20:04:07 +02:00
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system(sc_core::sc_module_name nm);
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virtual ~system();
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private:
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sc_core::sc_signal<sc_dt::sc_logic> s_ha, s_la, s_hb, s_lb, s_hc, s_lc;
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sc_core::sc_signal<bool> s_rst_n;
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sc_core::sc_signal<double> s_vref, s_va, s_vb, s_vc, s_vasens, s_vbsens, s_vcsens, s_vcentersens;
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2018-07-23 22:15:38 +02:00
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sc_core::sc_vector<sc_core::sc_signal<double>> s_ana;
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sysc::hifive1 i_hifive1;
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sysc::h_bridge i_h_bridge;
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sysc::dc_motor i_motor;
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void gen_por();
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};
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}
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2019-07-16 15:54:15 +02:00
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#endif /* __SYSC_TOP_SYSTEM_H_ */
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