2018-11-08 13:31:28 +01:00
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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2017-10-04 10:31:11 +02:00
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#include "sysc/SiFive/clint.h"
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2017-10-04 14:30:25 +02:00
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2017-11-10 22:40:24 +01:00
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#include "scc/report.h"
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2018-11-08 13:31:28 +01:00
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#include "scc/utilities.h"
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2017-10-04 10:31:11 +02:00
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#include "sysc/SiFive/gen/clint_regs.h"
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namespace sysc {
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2018-11-08 13:31:28 +01:00
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using namespace sc_core;
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2017-10-04 10:31:11 +02:00
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2019-06-28 20:59:16 +02:00
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const int lfclk_mutiplier = 1 ;//<< 12;
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2017-10-04 10:31:11 +02:00
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clint::clint(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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2018-07-12 15:27:36 +02:00
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, NAMED(tlclk_i)
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, NAMED(lfclk_i)
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2017-10-04 10:31:11 +02:00
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, NAMED(rst_i)
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, NAMED(mtime_int_o)
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, NAMED(msip_int_o)
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2018-11-08 13:31:28 +01:00
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, NAMEDD(regs, clint_regs)
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, cnt_fraction(0) {
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2019-06-28 20:59:16 +02:00
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SC_HAS_PROCESS(clint);// NOLINT
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mtime_i.bind(*this);
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2017-10-04 10:31:11 +02:00
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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2018-11-08 13:31:28 +01:00
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sensitive << tlclk_i << lfclk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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2019-06-28 20:59:16 +02:00
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SC_METHOD(mtime_evt_cb);
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sensitive<<mtime_evt;
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dont_initialize();
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2018-11-08 13:31:28 +01:00
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regs->mtimecmp.set_write_cb([this](scc::sc_register<uint64_t> ®, uint64_t data, sc_core::sc_time d) -> bool {
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if (!regs->in_reset()) {
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reg.put(data);
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2019-06-28 20:59:16 +02:00
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this->update_mtime(true);
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}
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->mtime.set_read_cb([this](const scc::sc_register<uint64_t> ®, uint64_t &data, sc_core::sc_time d) -> bool {
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2017-10-04 10:31:11 +02:00
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this->update_mtime();
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data = reg.get();
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->mtime.set_write_cb(
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[this](scc::sc_register<uint64_t> ®, uint64_t data, sc_core::sc_time d) -> bool { return false; });
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regs->msip.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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msip_int_o.write(regs->r_msip.msip);
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return true;
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});
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}
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void clint::clock_cb() {
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update_mtime();
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2018-07-12 15:27:36 +02:00
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clk = lfclk_i.read();
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update_mtime();
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}
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2018-11-08 13:31:28 +01:00
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clint::~clint() = default;
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2017-10-04 10:31:11 +02:00
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void clint::reset_cb() {
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if (rst_i.read()) {
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regs->reset_start();
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msip_int_o.write(false);
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mtime_int_o.write(false);
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cnt_fraction = 0;
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} else
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regs->reset_stop();
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}
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2019-06-28 20:59:16 +02:00
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void clint::mtime_evt_cb() {
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update_mtime();
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}
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void clint::update_mtime(bool force) {
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if (clk > SC_ZERO_TIME) {
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uint64_t elapsed_clks =
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(sc_time_stamp() - last_updt) / clk; // get the number of clock periods since last invocation
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last_updt += elapsed_clks * clk; // increment the last_updt timestamp by the number of clocks
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if (force || elapsed_clks) { // update mtime reg if we have more than 0 elapsed clk periods
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regs->r_mtime += elapsed_clks;
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2019-06-28 20:59:16 +02:00
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//mtime_evt.cancel();
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2018-07-12 15:27:36 +02:00
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if (regs->r_mtimecmp > 0)
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2018-11-08 13:31:28 +01:00
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if (regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) {
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sc_core::sc_time next_trigger =
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2019-06-28 20:59:16 +02:00
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(clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->r_mtime) - cnt_fraction * clk;
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2018-11-08 13:31:28 +01:00
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SCTRACE() << "Timer fires at " << sc_time_stamp() + next_trigger;
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2018-07-12 15:27:36 +02:00
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mtime_evt.notify(next_trigger);
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mtime_int_o.write(false);
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2019-06-28 20:59:16 +02:00
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} else {
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SCTRACE() << "Timer fired at " << sc_time_stamp();
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2018-07-12 15:27:36 +02:00
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mtime_int_o.write(true);
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2019-06-28 20:59:16 +02:00
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}
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2018-07-12 15:27:36 +02:00
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}
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} else
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last_updt = sc_time_stamp();
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2017-10-04 10:31:11 +02:00
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}
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2019-06-28 20:59:16 +02:00
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uint64_t clint::peek(tlm::tlm_tag<uint64_t>* t) const {
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const_cast<clint*>(this)->update_mtime();
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return regs->r_mtime;
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}
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bool clint::nb_peek(uint64_t& t) const {
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const_cast<clint*>(this)->update_mtime();
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t= regs->r_mtime;
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return true;
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}
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bool clint::nb_can_peek(tlm::tlm_tag<uint64_t>* t) const {
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return true;
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}
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const sc_core::sc_event& clint::ok_to_peek(tlm::tlm_tag<uint64_t>* t) const {
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return dummy_evt;
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}
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2017-10-04 10:31:11 +02:00
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} /* namespace sysc */
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2019-06-28 20:59:16 +02:00
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