HIFIVE1-VP/riscv.sc/gen_input/plic.rdl

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regfile plic_regs {
reg {
name="priority";
desc="interrupt source priority";
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field {} priority[2:0];
} priority[255] @0x004;
reg {
name="pending";
desc="pending irq";
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field {} pending[31:0];
} pending @0x1000;
reg {
name="enabled";
desc="enabled interrupts";
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field {} enabled[31:0];
} enabled @0x2000;
reg {
name="threshold";
desc="interrupt priority threshold";
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field {} \threshold[2:0];
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} \threshold @0x200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
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field {} interrupt_claimed[31:0];
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} claim_complete @0x200004;
};