HIFIVE1-VP/riscv.sc/gen_input/plic.rdl

regfile plic_regs {
	reg {
		name="priority";
		desc="interrupt source priority";
		field {} priority[2:0];
	} priority[255] @0x004;
	reg {
		name="pending";
		desc="pending irq";
		field {} pending[31:0];
	} pending @0x1000;
	reg {
		name="enabled";
		desc="enabled interrupts";
		field {} enabled[31:0];
	} enabled @0x2000;
	reg {
		name="threshold";
		desc="interrupt priority threshold";
		field {} \threshold[2:0];
	} \threshold @0x200000;
	reg {
		name="claim/complete";
		desc="interrupt handling completed";
		field {} interrupt_claimed[31:0];
	} claim_complete @0x200004;
};