309 lines
9.9 KiB
Plaintext
309 lines
9.9 KiB
Plaintext
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InsructionSet RV32IBase {
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constants {
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XLEN,
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XLEN_BIT_MASK,
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PCLEN,
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fence,
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fencei,
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fencevmal,
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fencevmau
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}
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address_spaces {
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MEM[8], CSR[XLEN], FENCE[XLEN]
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}
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registers {
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[31:0] X[XLEN],
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PC[XLEN](is_pc)
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}
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instructions {
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LUI{
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encoding: imm[31:12]s | rd[4:0] | b0110111;
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args_disass: "x%rd$d, 0x%imm$05x";
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if(rd!=0) X[rd] <= imm;
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}
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AUIPC{
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encoding: imm[31:12]s | rd[4:0] | b0010111;
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args_disass: "x%rd%, 0x%imm$08x";
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if(rd!=0) X[rd] <= PC+imm;
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}
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JAL(no_cont){
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encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
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args_disass: "x%rd$d, 0x%imm$x";
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if(rd!=0) X[rd] <= PC+4;
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PC<=PC+imm;
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}
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JALR(no_cont){
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
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args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
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if(rd!=0) X[rd] <= PC+4;
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val ret[XLEN] <= X[rs1]+ imm;
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PC<=ret& ~0x1;
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}
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BEQ(no_cont){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
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}
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BNE(no_cont){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
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}
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BLT(no_cont){
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
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}
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BGE(no_cont) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
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}
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BLTU(no_cont) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
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}
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BGEU(no_cont) {
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encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
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args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
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PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
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}
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LB {
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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if(rd!=0) X[rd]<=sext(MEM[offs]);
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}
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LH {
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encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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if(rd!=0) X[rd]<=sext(MEM[offs]{16});
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}
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LW {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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if(rd!=0) X[rd]<=sext(MEM[offs]{32});
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}
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LBU {
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encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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if(rd!=0) X[rd]<=zext(MEM[offs]);
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}
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LHU {
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encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
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args_disass:"x%rd$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1]+imm;
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if(rd!=0) X[rd]<=zext(MEM[offs]{16});
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}
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SB {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1] + imm;
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MEM[offs] <= X[rs2];
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}
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SH {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1] + imm;
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MEM[offs]{16} <= X[rs2];
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}
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SW {
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encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
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args_disass:"x%rs2$d, %imm%(x%rs1$d)";
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val offs[XLEN] <= X[rs1] + imm;
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MEM[offs]{32} <= X[rs2];
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}
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ADDI {
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encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if(rd != 0) X[rd] <= X[rs1] + imm;
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}
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SLTI {
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encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); //TODO: needs fix
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}
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SLTIU {
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encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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val full_imm[XLEN] <= imm's;
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if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
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}
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XORI {
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encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if(rd != 0) X[rd] <= X[rs1] ^ imm;
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}
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ORI {
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encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if(rd != 0) X[rd] <= X[rs1] | imm;
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}
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ANDI {
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encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %imm%";
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if(rd != 0) X[rd] <= X[rs1] & imm;
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}
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SLLI {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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if(rd != 0) X[rd] <= shll(X[rs1], shamt);
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}
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SRLI {
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encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
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}
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SRAI {
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encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
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args_disass:"x%rd$d, x%rs1$d, %shamt%";
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if(rd != 0) X[rd] <= shra(X[rs1], shamt);
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}
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ADD {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] + X[rs2];
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}
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SUB {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] - X[rs2];
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}
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SLL {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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SLT {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0);
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}
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SLTU {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0);
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}
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XOR {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] ^ X[rs2];
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}
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SRL {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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SRA {
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encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK);
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}
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OR {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] | X[rs2];
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}
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AND {
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encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0) X[rd] <= X[rs1] & X[rs2];
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}
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FENCE {
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encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111;
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FENCE[fence] <= pred<<4 | succ;
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}
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FENCE_I(flush) {
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encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ;
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FENCE[fencei] <= imm;
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}
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ECALL(no_cont) {
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encoding: b000000000000 | b00000 | b000 | b00000 | b1110011;
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raise(0, 11);
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}
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EBREAK(no_cont) {
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encoding: b000000000001 | b00000 | b000 | b00000 | b1110011;
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raise(0, 3);
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}
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URET(no_cont) {
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encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011;
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leave(0);
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}
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SRET(no_cont) {
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encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011;
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leave(1);
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}
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MRET(no_cont) {
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encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011;
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leave(3);
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}
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WFI {
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encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011;
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wait(1);
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}
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SFENCE.VMA {
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encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011;
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FENCE[fencevmal] <= rs1;
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FENCE[fencevmau] <= rs2;
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}
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CSRRW {
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encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, x%rs1$d";
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val rs_val[XLEN] <= X[rs1];
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if(rd!=0){
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val csr_val[XLEN] <= CSR[csr];
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CSR[csr] <= rs_val;
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// make sure Xrd is updated once CSR write succeeds
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X[rd] <= csr_val;
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} else {
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CSR[csr] <= rs_val;
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}
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}
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CSRRS {
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encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, x%rs1$d";
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val xrd[XLEN] <= CSR[csr];
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val xrs1[XLEN] <= X[rs1];
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if(rd!=0) X[rd] <= xrd;
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if(rs1!=0) CSR[csr] <= xrd | xrs1;
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}
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CSRRC {
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encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, x%rs1$d";
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val xrd[XLEN] <= CSR[csr];
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val xrs1[XLEN] <= X[rs1];
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if(rd!=0) X[rd] <= xrd;
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if(rs1!=0) CSR[csr] <= xrd & ~xrs1;
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}
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CSRRWI {
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encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
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if(rd!=0) X[rd] <= CSR[csr];
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CSR[csr] <= zext(zimm);
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}
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CSRRSI {
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encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
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val res[XLEN] <= CSR[csr];
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if(zimm!=0) CSR[csr] <= res | zext(zimm);
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// make sure rd is written after csr write succeeds
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if(rd!=0) X[rd] <= res;
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}
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CSRRCI {
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encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011;
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args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
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val res[XLEN] <= CSR[csr];
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if(rd!=0) X[rd] <= res;
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if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN);
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}
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}
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}
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