74 lines
1.0 KiB
YAML
74 lines
1.0 KiB
YAML
# VexRiscv
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- operation: RdCustReg
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earliest: 1
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latency: 0
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latest: 3
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- operation: WrCustReg.addr
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earliest: 1
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latency: 0
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latest: 1
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- operation: WrCustReg.data
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earliest: 1
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latency: 1
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costly: 2
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- operation: RdRS1
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earliest: 2
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latency: 0
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latest: 3
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costly: 4
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- operation: RdRS2
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earliest: 2
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latency: 0
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latest: 3
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costly: 4
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- operation: WrRD
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earliest: 2
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latency: 1
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costly: 3
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- operation: RdPC
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earliest: 1
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latency: 0
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costly: 4
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- operation: WrPC
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earliest: 0
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latency: 0
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costly: 1
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- operation: RdMem
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earliest: 2
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latency: 1
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costly: 3
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- operation: WrMem
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earliest: 2
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latency: 1
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costly: 3
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- operation: RdIValid
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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- operation: RdInstr
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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- operation: RdStall
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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- operation: WrStall
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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- operation: RdFlush
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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- operation: WrFlush
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earliest: 1
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latency: 0
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latest: 3
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costly: 4
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