79 lines
2.7 KiB
Plaintext
79 lines
2.7 KiB
Plaintext
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InstructionSet Zxlwc_ascon {
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architectural_state {
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unsigned int XLEN=32;
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register unsigned<XLEN> X[32] [[is_main_reg]];
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}
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functions {
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unsigned<64> _ror64(unsigned<64> val, unsigned<64> shift_amount) {
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return (val >> shift_amount) | (val << (64 - shift_amount));
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}
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// ROT_0 = { 19, 61, 1, 10, 7 }
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unsigned<64> rot_0(unsigned<5> imm){
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unsigned<64> ret;
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if(imm == 0)
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ret = 19;
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else if(imm==1)
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ret = 61;
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else if(imm==2)
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ret = 1;
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else if(imm==3)
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ret = 10;
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else if(imm==4)
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ret = 7;
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else ret = 0;
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return ret;
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}
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// ROT_1 = { 28, 39, 6, 17, 41 }
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unsigned<64> rot_1(unsigned<5> imm){
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unsigned<64> ret;
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if(imm == 0)
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ret = 28;
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else if(imm==1)
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ret = 39;
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else if(imm==2)
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ret = 6;
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else if(imm==3)
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ret = 17;
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else if(imm==4)
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ret = 41;
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else ret = 0;
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return ret;
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}
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}
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instructions{
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ASCON_SIGMA_LO [[enable=XLEN==32]] {
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encoding: 2'b00 :: imm[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0101011;
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behavior: {
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unsigned<32> x_hi = (unsigned<32>)X[rs2];
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unsigned<32> x_lo = (unsigned<32>)X[rs1];
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unsigned<64> x = x_hi :: x_lo;
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unsigned<64> r = x ^ _ror64(x, rot_0(imm)) ^ _ror64(x, rot_1(imm));
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X[rd] = (unsigned<XLEN>)r[31:0];
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}
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}
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ASCON_SIGMA_HI [[enable=XLEN==32]] {
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encoding: 2'b01 :: imm[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0101011;
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behavior: {
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unsigned<32> x_hi = (unsigned<32>)X[rs2];
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unsigned<32> x_lo = (unsigned<32>)X[rs1];
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unsigned<64> x = x_hi :: x_lo;
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unsigned<64> r = x ^ _ror64(x, rot_0(imm)) ^ _ror64(x, rot_1(imm));
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X[rd] = (unsigned<XLEN>)r[63:32];
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}
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}
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ASCON_SIGMA [[enable=XLEN==64]] {
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encoding: 2'b10 :: imm[4:0] :: 5'b00000 :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0101011;
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behavior: {
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unsigned<64> x = X[rs1];
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unsigned<64> r = x ^ _ror64(x, rot_0(imm)) ^ _ror64(x, rot_1(imm));
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X[rd] = (unsigned<XLEN>)r;
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}
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}
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}
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} |