add keccak example (WIP)
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257
wsTemplate/examples/Keccak.core_desc
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257
wsTemplate/examples/Keccak.core_desc
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InstructionSet Zx_keccak {
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architectural_state {
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unsigned int XLEN=32;
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register unsigned<XLEN> X[32] [[is_main_reg]];
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extern unsigned<8> MEM[1 << XLEN] [[is_main_mem]];
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const unsigned int RV_CAUSE_ILLEGAL_INSTRUCTION = 0x02;
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register unsigned<64> K[32];
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register unsigned<8> LFSR;
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}
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functions {
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unsigned<64> ROL64(unsigned<64> val, unsigned<64> shift) {
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return (val << shift) | (val >> (64 - shift));
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}
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unsigned<64> readLane(unsigned int x, unsigned int y) {
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return K[x + 5 * y];
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}
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unsigned<64> XORLane(unsigned int x, unsigned int y, unsigned<64> value) {
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K[x + 5 * y] = K[x + 5 * y] ^ value;
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return 0;
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}
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unsigned<64> writeLane(unsigned int x, unsigned int y, unsigned<64> value) {
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K[x + 5 * y] = value;
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return 0;
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}
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unsigned<1> LFSR86540() {
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unsigned<1> result = (unsigned<1>)(LFSR & 0x01);
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if ((LFSR & 0x80) != 0) {
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// Primitive polynomial over GF(2): x^8+x^6+x^5+x^4+1
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LFSR = (LFSR << 1) ^ 0x71;
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} else {
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LFSR = LFSR << 1;
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}
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return result;
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}
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}
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instructions {
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// Custom-0 Opcode
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LK64 {
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encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011;
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assembly: "{name(rd)}, {imm}({name(rs1)})";
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behavior: {
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unsigned<XLEN> load_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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K[rd]= MEM[load_address+7:load_address];
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}
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}
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LK128 {
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encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0001011;
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assembly: "{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd%2 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<2; i++){
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unsigned<XLEN> load_address = (unsigned<XLEN>)(base_address + 8*i);
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K[rd+i]= MEM[load_address+7:load_address];
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}
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}
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}
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LK256 {
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encoding: imm[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0001011;
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assembly: "{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd%4 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<4; i++){
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unsigned<XLEN> load_address = (unsigned<XLEN>)(base_address + 8*i);
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K[rd+i]= MEM[load_address+7:load_address];
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}
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}
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}
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LK512 {
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encoding: imm[11:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0001011;
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assembly: "{name(rd)}, {imm}({name(rs1)})";
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behavior: if(rd%8 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<8; i++){
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unsigned<XLEN> load_address = (unsigned<XLEN>)(base_address + 8*i);
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K[rd+i]= MEM[load_address+7:load_address];
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}
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}
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}
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SK64 {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: imm[4:0] :: 7'b0001011;
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assembly: "{name(rs2)}, {imm}({name(rs1)})";
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behavior: {
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unsigned<XLEN> store_address = (unsigned<XLEN>)(X[rs1] + (signed)imm);
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MEM[store_address+7:store_address] = K[rs2];
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}
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}
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SK128 {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: imm[4:0] :: 7'b0001011;
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assembly: "{name(rs2)}, {imm}({name(rs1)})";
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behavior: if(rs2%2 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<2; i++){
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unsigned<XLEN> store_address = (unsigned<XLEN>)(base_address + 8*i);
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MEM[store_address+7:store_address] = K[rs2+i];
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}
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}
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}
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SK256 {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: imm[4:0] :: 7'b0001011;
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assembly: "{name(rs2)}, {imm}({name(rs1)})";
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behavior: if(rs2%4 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<4; i++){
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unsigned<XLEN> store_address = (unsigned<XLEN>)(base_address + 8*i);
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MEM[store_address+7:store_address] = K[rs2+i];
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}
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}
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}
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SK512 {
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encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: imm[4:0] :: 7'b0001011;
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assembly: "{name(rs2)}, {imm}({name(rs1)})";
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behavior: if(rs2%8 == 1) ; else {
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unsigned<XLEN> base_address = (unsigned<XLEN>)(X[rs1] + (signed<12>)imm);
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for(unsigned int i = 0; i<8; i++){
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unsigned<XLEN> store_address = (unsigned<XLEN>)(base_address + 8*i);
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MEM[store_address+7:store_address] = K[rs2+i];
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}
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}
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}
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KECCAK_THETA {
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encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b000 :: 5'b00000 :: 7'b0001011;
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assembly: "keccak.theta";
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behavior: {
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// Temporary storage for C array (5 columns)
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unsigned<64> C0, C1, C2, C3, C4;
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unsigned<64> D;
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// Compute the parity of the columns
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C0 = readLane(0, 0) ^ readLane(0, 1) ^ readLane(0, 2) ^ readLane(0, 3) ^ readLane(0, 4);
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C1 = readLane(1, 0) ^ readLane(1, 1) ^ readLane(1, 2) ^ readLane(1, 3) ^ readLane(1, 4);
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C2 = readLane(2, 0) ^ readLane(2, 1) ^ readLane(2, 2) ^ readLane(2, 3) ^ readLane(2, 4);
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C3 = readLane(3, 0) ^ readLane(3, 1) ^ readLane(3, 2) ^ readLane(3, 3) ^ readLane(3, 4);
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C4 = readLane(4, 0) ^ readLane(4, 1) ^ readLane(4, 2) ^ readLane(4, 3) ^ readLane(4, 4);
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// Apply theta effect to column 0
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D = C4 ^ ROL64(C1, 1);
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XORLane(0, 0, D);
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XORLane(0, 1, D);
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XORLane(0, 2, D);
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XORLane(0, 3, D);
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XORLane(0, 4, D);
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// Apply theta effect to column 1
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D = C0 ^ ROL64(C2, 1);
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XORLane(1, 0, D);
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XORLane(1, 1, D);
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XORLane(1, 2, D);
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XORLane(1, 3, D);
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XORLane(1, 4, D);
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// Apply theta effect to column 2
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D = C1 ^ ROL64(C3, 1);
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XORLane(2, 0, D);
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XORLane(2, 1, D);
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XORLane(2, 2, D);
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XORLane(2, 3, D);
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XORLane(2, 4, D);
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// Apply theta effect to column 3
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D = C2 ^ ROL64(C4, 1);
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XORLane(3, 0, D);
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XORLane(3, 1, D);
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XORLane(3, 2, D);
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XORLane(3, 3, D);
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XORLane(3, 4, D);
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// Apply theta effect to column 4
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D = C3 ^ ROL64(C0, 1);
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XORLane(4, 0, D);
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XORLane(4, 1, D);
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XORLane(4, 2, D);
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XORLane(4, 3, D);
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XORLane(4, 4, D);
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}
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}
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KECCAK_RHO_PI {
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encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b001 :: 5'b00000 :: 7'b0001011;
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assembly: "keccak.rhopi";
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behavior: {
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unsigned<64> current, temp;
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unsigned int x, y;
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unsigned int r;
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unsigned int Y;
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// Start at coordinates (1, 0)
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x = 1;
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y = 0;
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current = readLane(x, y);
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// Iterate over ((0 1)(2 3))^t * (1 0) for 0 ≤ t ≤ 23
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for(unsigned int t = 0; t < 24; t++) {
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// Compute the rotation constant r = (t+1)(t+2)/2
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r = ((t + 1) * (t + 2) / 2) % 64;
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// Compute ((0 1)(2 3)) * (x y)
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Y = (2 * x + 3 * y) % 5;
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x = y;
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y = Y;
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// Swap current and state(x,y), and rotate
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temp = readLane(x, y);
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writeLane(x, y, ROL64(current, r));
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current = temp;
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}
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}
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}
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KECCAK_CHI {
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encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b010 :: 5'b00000 :: 7'b0001011;
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assembly: "keccak.chi";
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behavior: {
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unsigned<64> T0, T1, T2, T3, T4;
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unsigned int y;
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for(y = 0; y < 5; y++) {
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/* Take a copy of the plane */
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T0 = readLane(0, y);
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T1 = readLane(1, y);
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T2 = readLane(2, y);
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T3 = readLane(3, y);
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T4 = readLane(4, y);
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/* Compute χ on the plane */
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writeLane(0, y, T0 ^ (~T1 & T2));
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writeLane(1, y, T1 ^ (~T2 & T3));
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writeLane(2, y, T2 ^ (~T3 & T4));
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writeLane(3, y, T3 ^ (~T4 & T0));
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writeLane(4, y, T4 ^ (~T0 & T1));
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}
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}
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}
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KECCAK_IOTA {
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encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b011 :: 5'b00000 :: 7'b0001011;
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assembly: "keccak.iota";
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behavior: {
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unsigned int j;
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for (j = 0; j < 7; j++) {
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unsigned int bitPosition = (unsigned int)((1 << j) - 1);
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if (LFSR86540()) {
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XORLane(0, 0, (unsigned<64>)1 << bitPosition);
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}
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}
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}
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}
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KECCAK_LFSR_RESET {
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encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b100 :: 5'b00000 :: 7'b0001011;
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assembly: "keccak.lfsr.reset";
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behavior: {
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LFSR = 0x01;
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}
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}
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}
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}
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