update to latest cppyy

pysysc/sccppyy.py

@@ -150,7 +150,7 @@ def add_sys_include_path(incl):
 def _pythonizor(clazz, name):
     # A pythonizor receives the freshly prepared bound C++ class, and a name stripped down to
     # the namespace the pythonizor is applied. Also accessible are clazz.__name__ (for the
-    # Python name) and clazz.__cppname__ (for the C++ name)
+    # Python name) and clazz.__cpp_name__ (for the C++ name)
     if name == 'sc_time':
         clazz.__repr__ = lambda self: repr(self.to_string())
         clazz.__str__ = lambda self: self.to_string()

pysysc/structural.py

@@ -15,6 +15,53 @@ class Mode(Enum):
 
 mode=Mode.SIM
 
+module_list = list()
+connection_list = list()
+
+def dump_structure():
+    mports=dict()
+    
+    def add_port(p, io):
+        mod = p.get_parent_object()
+        if mod not in mports:
+            mports[mod]=dict()
+            mports[mod]['in']=[]
+            mports[mod]['out']=[]
+        if not p in mports[mod][io]:
+            mports[mod][io].append(p)
+        
+    for c in connection_list:
+        add_port(c.source, 'out')
+        for t in c.targets:
+            add_port(t, 'in')
+        
+    with open("structure.dot", "w") as f:
+        f.write("""digraph structs {
+    rankdir=LR
+    node [shape=record];\n""")
+        for m in mports.keys():
+            #struct3 [shape=record,label="hello\nworld |{ b |{c|<here> d|e}| f}| g | h"];
+            in_names=['<%s> %s'%(p.basename(), p.basename()) for p in mports[m]['in']]
+            out_names=['<%s> %s'%(p.basename(), p.basename()) for p in mports[m]['out']]
+            if len(in_names) == 0:
+                f.write('  %s [shape=record,label="{%s|{%s}}"];\n' % (
+                    m.name(), m.basename(), '|'.join(out_names)))
+            elif len(out_names) == 0:
+                f.write('  %s [shape=record,label="{{%s}|%s}"];\n' % (
+                    m.name(), '|'.join(in_names), m.basename()))
+            else:
+                f.write('  %s [shape=record,label="{{%s}|%s|{%s}}"];\n' % (
+                    m.name(), '|'.join(in_names), m.basename(), '|'.join(out_names)))
+        for c in connection_list:
+            attr = 'dir=both arrowhead=box arrowtail=obox'
+            if isinstance(c, Signal):
+                attr = 'dir=none'
+            src = '%s:%s' % (c.source.get_parent_object().name(), c.source.basename())
+            for t in c.targets:
+                tgt = '%s:%s' % (t.get_parent_object().name(), t.basename())
+                f.write("    %s -> %s [%s];\n" % (src, tgt, attr))
+        f.write("}\n")
+        
 class Simulation(object):
     
     @staticmethod
@@ -74,6 +121,7 @@ class Module(object):
     def __init__(self, clazz):
         self.cppclazz=clazz
         self.instance=None
+        module_list.append(self)
     
     def __getattr__(self, attr):
         if self.instance is None:
@@ -91,6 +139,7 @@ class Connection(object):
     def __init__(self):
         self.source=None
         self.targets=[]
+        connection_list.append(self)
     
     def src(self, module_port):
         self.source=module_port
@@ -101,6 +150,11 @@ class Connection(object):
         self.source.bind(module_port)
         return self
 
+    def cross(self, module_port_in, module_port_out):
+        self.targets.append(module_port_in)
+        self.source.bind(module_port_in)
+        return Connection().src(module_port_out)
+        
 class Signal(Connection):
     '''
     classdocs
@@ -118,7 +172,7 @@ class Signal(Connection):
         
     def src(self, module_port):
         self.source=module_port
-        port_class_name=type(module_port).__cppname__
+        port_class_name=type(module_port).__cpp_name__
         match = self._sc_inout_re.match(port_class_name)
         if match:
             self.data_type=match.group(1)
@@ -138,3 +192,7 @@ class Signal(Connection):
         module_port.bind(self.signal)
         return self
         
+    def cross(self, module_port_in, module_port_out):
+        self.targets.append(module_port_in)
+        self.source.bind(module_port_in)
+        return Signal().src(module_port_out)