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https://github.com/riscv-software-src/opensbi.git
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f95d1140f6
If a property value is too small, len will be zero after the division on the next line, so the property will be ignored. This is the same behavior as when the length check fails. Furthermore, the first two length checks were already ineffectual, because each item in those arrays is 12 bytes long, not 8. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
// SPDX-License-Identifier: BSD-2-Clause
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/*
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* fdt_pmu.c - Flat Device Tree PMU helper routines
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Atish Patra <atish.patra@wdc.com>
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*/
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#include <libfdt.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_pmu.h>
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#include <sbi/sbi_scratch.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_pmu.h>
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#define FDT_PMU_HW_EVENT_MAX (SBI_PMU_HW_EVENT_MAX * 2)
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struct fdt_pmu_hw_event_select_map fdt_pmu_evt_select[FDT_PMU_HW_EVENT_MAX] = {0};
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uint32_t hw_event_count;
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uint64_t fdt_pmu_get_select_value(uint32_t event_idx)
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{
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int i;
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struct fdt_pmu_hw_event_select_map *event;
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for (i = 0; i < hw_event_count; i++) {
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event = &fdt_pmu_evt_select[i];
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if (event->eidx == event_idx)
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return event->select;
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}
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return 0;
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}
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int fdt_pmu_fixup(void *fdt)
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{
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int pmu_offset;
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struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
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if (!fdt)
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return SBI_EINVAL;
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pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
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if (pmu_offset < 0)
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return SBI_EFAIL;
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fdt_delprop(fdt, pmu_offset, "riscv,event-to-mhpmcounters");
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fdt_delprop(fdt, pmu_offset, "riscv,event-to-mhpmevent");
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fdt_delprop(fdt, pmu_offset, "riscv,raw-event-to-mhpmcounters");
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if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
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fdt_delprop(fdt, pmu_offset, "interrupts-extended");
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return 0;
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}
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int fdt_pmu_setup(const void *fdt)
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{
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int i, pmu_offset, len, result;
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const u32 *event_val;
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const u32 *event_ctr_map;
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struct fdt_pmu_hw_event_select_map *event;
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uint64_t raw_selector, select_mask;
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u32 event_idx_start, event_idx_end, ctr_map;
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if (!fdt)
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return SBI_EINVAL;
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pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
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if (pmu_offset < 0)
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return SBI_ENOENT;
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event_ctr_map = fdt_getprop(fdt, pmu_offset,
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"riscv,event-to-mhpmcounters", &len);
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if (event_ctr_map) {
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len = len / (sizeof(u32) * 3);
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for (i = 0; i < len; i++) {
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event_idx_start = fdt32_to_cpu(event_ctr_map[3 * i]);
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event_idx_end = fdt32_to_cpu(event_ctr_map[3 * i + 1]);
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ctr_map = fdt32_to_cpu(event_ctr_map[3 * i + 2]);
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result = sbi_pmu_add_hw_event_counter_map(
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event_idx_start, event_idx_end, ctr_map);
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if (result)
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return result;
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}
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}
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event_val = fdt_getprop(fdt, pmu_offset,
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"riscv,event-to-mhpmevent", &len);
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if (event_val) {
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len = len / (sizeof(u32) * 3);
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for (i = 0; i < len; i++) {
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event = &fdt_pmu_evt_select[hw_event_count];
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event->eidx = fdt32_to_cpu(event_val[3 * i]);
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event->select = fdt32_to_cpu(event_val[3 * i + 1]);
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event->select = (event->select << 32) |
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fdt32_to_cpu(event_val[3 * i + 2]);
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hw_event_count++;
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}
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}
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event_val = fdt_getprop(fdt, pmu_offset,
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"riscv,raw-event-to-mhpmcounters", &len);
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if (event_val) {
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len = len / (sizeof(u32) * 5);
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for (i = 0; i < len; i++) {
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raw_selector = fdt32_to_cpu(event_val[5 * i]);
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raw_selector = (raw_selector << 32) |
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fdt32_to_cpu(event_val[5 * i + 1]);
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select_mask = fdt32_to_cpu(event_val[5 * i + 2]);
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select_mask = (select_mask << 32) |
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fdt32_to_cpu(event_val[5 * i + 3]);
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ctr_map = fdt32_to_cpu(event_val[5 * i + 4]);
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result = sbi_pmu_add_raw_event_counter_map(
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raw_selector, select_mask, ctr_map);
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if (result)
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return result;
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}
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}
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return 0;
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}
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