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f6fa62bd16
The "RISC-V C API" [1] defines architecture extension test macros says naming rule for the test macros is __riscv_<ext_name>, where <ext_name> is all lower-case. Three extensions dealing with atomics implementation are: "zaamo" consists of AMO instructions, "zalrsc" - LR/SC, "a" extension means both "zaamo" and "zalrsc" Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc. Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated. Use correct test macro __riscv_zaamo for the AMO variant of atomics. It used to be __riscv_atomic that is both deprecated and incorrect because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc" If ISA enables only zaamo but not zalrsc, code as it was would not compile. Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so query __riscv_atomic - it should be treated as both __riscv_zaamo and __riscv_zalrsc, in all present cases __riscv_zaamo is more favorable so take is as alternative for __riscv_zaamo [1] https://github.com/riscv-non-isa/riscv-c-api-doc Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
87 lines
1.9 KiB
C
87 lines
1.9 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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* Copyright (c) 2021 Christoph Müllner <cmuellner@linux.com>
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*/
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#include <sbi/riscv_barrier.h>
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#include <sbi/riscv_locks.h>
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static inline bool spin_lock_unlocked(spinlock_t lock)
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{
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return lock.owner == lock.next;
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}
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bool spin_lock_check(spinlock_t *lock)
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{
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RISCV_FENCE(r, rw);
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return !spin_lock_unlocked(*lock);
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}
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bool spin_trylock(spinlock_t *lock)
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{
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unsigned long inc = 1u << TICKET_SHIFT;
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unsigned long mask = 0xffffu << TICKET_SHIFT;
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u32 l0, tmp1, tmp2;
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__asm__ __volatile__(
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/* Get the current lock counters. */
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"1: lr.w.aq %0, %3\n"
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" slli %2, %0, %6\n"
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" and %2, %2, %5\n"
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" and %1, %0, %5\n"
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/* Is the lock free right now? */
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" bne %1, %2, 2f\n"
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" add %0, %0, %4\n"
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/* Acquire the lock. */
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" sc.w.rl %0, %0, %3\n"
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" bnez %0, 1b\n"
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"2:"
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: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
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: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
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: "memory");
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return l0 == 0;
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}
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void spin_lock(spinlock_t *lock)
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{
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unsigned long inc = 1u << TICKET_SHIFT;
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unsigned long mask = 0xffffu;
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u32 l0, tmp1, tmp2;
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__asm__ __volatile__(
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/* Atomically increment the next ticket. */
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#if defined(__riscv_atomic) || defined(__riscv_zaamo)
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" amoadd.w.aqrl %0, %4, %3\n"
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#elif defined(__riscv_zalrsc)
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"3: lr.w.aqrl %0, %3\n"
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" addw %1, %0, %4\n"
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" sc.w.aqrl %1, %1, %3\n"
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" bnez %1, 3b\n"
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#else
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#error "need A or Zaamo or Zalrsc"
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#endif
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/* Did we get the lock? */
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" srli %1, %0, %6\n"
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" and %1, %1, %5\n"
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"1: and %2, %0, %5\n"
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" beq %1, %2, 2f\n"
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/* If not, then spin on the lock. */
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" lw %0, %3\n"
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RISCV_ACQUIRE_BARRIER
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" j 1b\n"
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"2:"
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: "=&r"(l0), "=&r"(tmp1), "=&r"(tmp2), "+A"(*lock)
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: "r"(inc), "r"(mask), "I"(TICKET_SHIFT)
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: "memory");
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}
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void spin_unlock(spinlock_t *lock)
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{
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__smp_store_release(&lock->owner, lock->owner + 1);
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}
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