mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-08-24 15:31:22 +01:00

Clearing MIP at that point means that we can probably lose a pending interrupt. This should not happen, remove MIP clearing from there. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250519083950.739044-3-cleger@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>