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eeab500a65
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
16 lines
390 B
C
16 lines
390 B
C
// SPDX-License-Identifier: BSD-2-Clause
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#ifndef _RISCV_ANDES_SBI_H
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#define _RISCV_ANDES_SBI_H
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#include <sbi/sbi_trap.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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int andes_sbi_vendor_ext_provider(long funcid,
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const struct sbi_trap_regs *regs,
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unsigned long *out_value,
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struct sbi_trap_info *out_trap,
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const struct fdt_match *match);
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#endif /* _RISCV_ANDES_SBI_H */
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