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https://github.com/riscv-software-src/opensbi.git
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eeab500a65
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
// SPDX-License-Identifier: BSD-2-Clause
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/*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*
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*/
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#include <andes/andes45.h>
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#include <andes/andes_sbi.h>
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#include <sbi/riscv_asm.h>
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#include <sbi/sbi_error.h>
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enum sbi_ext_andes_fid {
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SBI_EXT_ANDES_FID0 = 0, /* Reserved for future use */
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SBI_EXT_ANDES_IOCP_SW_WORKAROUND,
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};
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static bool andes45_cache_controllable(void)
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{
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return (((csr_read(CSR_MICM_CFG) & MICM_CFG_ISZ_MASK) ||
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(csr_read(CSR_MDCM_CFG) & MDCM_CFG_DSZ_MASK)) &&
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(csr_read(CSR_MMSC_CFG) & MMSC_CFG_CCTLCSR_MASK) &&
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(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_CCTL_SUEN_MASK) &&
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misa_extension('U'));
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}
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static bool andes45_iocp_disabled(void)
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{
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return (csr_read(CSR_MMSC_CFG) & MMSC_IOCP_MASK) ? false : true;
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}
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static bool andes45_apply_iocp_sw_workaround(void)
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{
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return andes45_cache_controllable() & andes45_iocp_disabled();
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}
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int andes_sbi_vendor_ext_provider(long funcid,
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const struct sbi_trap_regs *regs,
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unsigned long *out_value,
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struct sbi_trap_info *out_trap,
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const struct fdt_match *match)
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{
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switch (funcid) {
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case SBI_EXT_ANDES_IOCP_SW_WORKAROUND:
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*out_value = andes45_apply_iocp_sw_workaround();
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break;
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default:
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return SBI_EINVAL;
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}
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return 0;
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}
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