mirror of
https://github.com/riscv-software-src/opensbi.git
synced 2025-12-15 19:51:49 +00:00
ec51e91eaa
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
73 lines
1.9 KiB
Plaintext
73 lines
1.9 KiB
Plaintext
CONFIG_PLATFORM_ALLWINNER_D1=y
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CONFIG_PLATFORM_ANDES_AE350=y
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CONFIG_PLATFORM_ANDES_QILAI=y
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CONFIG_PLATFORM_OPENHWGROUP_ARIANE=y
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CONFIG_PLATFORM_OPENHWGROUP_OPENPITON=y
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CONFIG_PLATFORM_RENESAS_RZFIVE=y
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CONFIG_PLATFORM_SIFIVE_FU540=y
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CONFIG_PLATFORM_SIFIVE_FU740=y
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CONFIG_PLATFORM_SOPHGO_SG2042=y
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CONFIG_PLATFORM_STARFIVE_JH7110=y
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CONFIG_PLATFORM_THEAD=y
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CONFIG_PLATFORM_MIPS_P8700=y
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CONFIG_PLATFORM_SPACEMIT_K1=y
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CONFIG_FDT_CACHE=y
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CONFIG_FDT_CACHE_SIFIVE_CCACHE=y
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CONFIG_FDT_CACHE_SIFIVE_PL2=y
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CONFIG_FDT_CPPC=y
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CONFIG_FDT_CPPC_RPMI=y
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CONFIG_FDT_GPIO=y
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CONFIG_FDT_GPIO_DESIGNWARE=y
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CONFIG_FDT_GPIO_SIFIVE=y
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CONFIG_FDT_GPIO_STARFIVE=y
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CONFIG_FDT_HSM=y
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CONFIG_FDT_HSM_RPMI=y
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CONFIG_FDT_HSM_SIFIVE_TMC0=y
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CONFIG_FDT_I2C=y
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CONFIG_FDT_I2C_SIFIVE=y
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CONFIG_FDT_I2C_DW=y
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CONFIG_FDT_IPI=y
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CONFIG_FDT_IPI_MSWI=y
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CONFIG_FDT_IPI_PLICSW=y
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CONFIG_FDT_IRQCHIP=y
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CONFIG_FDT_IRQCHIP_APLIC=y
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CONFIG_FDT_IRQCHIP_IMSIC=y
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CONFIG_FDT_IRQCHIP_PLIC=y
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CONFIG_FDT_MAILBOX=y
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CONFIG_RPMI_MAILBOX=y
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CONFIG_FDT_MAILBOX_RPMI_SHMEM=y
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CONFIG_FDT_REGMAP=y
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CONFIG_FDT_REGMAP_SYSCON=y
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CONFIG_FDT_RESET=y
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CONFIG_FDT_RESET_ATCWDT200=y
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CONFIG_FDT_RESET_GPIO=y
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CONFIG_FDT_RESET_HTIF=y
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CONFIG_FDT_RESET_RPMI=y
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CONFIG_FDT_RESET_SG2042_HWMON_MCU=y
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CONFIG_FDT_RESET_SUNXI_WDT=y
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CONFIG_FDT_RESET_SYSCON=y
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CONFIG_FDT_SERIAL=y
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CONFIG_FDT_SERIAL_CADENCE=y
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CONFIG_FDT_SERIAL_GAISLER=y
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CONFIG_FDT_SERIAL_HTIF=y
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CONFIG_FDT_SERIAL_RENESAS_SCIF=y
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CONFIG_FDT_SERIAL_SHAKTI=y
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CONFIG_FDT_SERIAL_SIFIVE=y
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CONFIG_FDT_SERIAL_LITEX=y
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CONFIG_FDT_SERIAL_UART8250=y
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CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
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CONFIG_SERIAL_SEMIHOSTING=y
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CONFIG_FDT_SUSPEND=y
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CONFIG_FDT_SUSPEND_RPMI=y
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CONFIG_FDT_SUSPEND_SIFIVE_SMC0=y
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CONFIG_FDT_TIMER=y
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CONFIG_FDT_TIMER_MTIMER=y
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CONFIG_FDT_TIMER_PLMT=y
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CONFIG_FDT_MPXY=y
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CONFIG_FDT_MPXY_RPMI_MBOX=y
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CONFIG_FDT_MPXY_RPMI_CLOCK=y
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CONFIG_FDT_MPXY_RPMI_VOLTAGE=y
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CONFIG_FDT_MPXY_RPMI_DEVICE_POWER=y
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CONFIG_FDT_MPXY_RPMI_PERFORMANCE=y
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CONFIG_FDT_MPXY_RPMI_SYSMSI=y
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